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* new nodes should be added to the worklist, not old nodes.Chris Lattner2009-01-161-1/+2
| | | | llvm-svn: 62359
* CreateVirtualRegisters does trivial copy coalescing. If a node def is used ↵Evan Cheng2009-01-162-56/+63
| | | | | | by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. llvm-svn: 62356
* Registry.h should not depend on CommandLine.h.Mikhail Glushenkov2009-01-161-0/+1
| | | | | | | Split Support/Registry.h into two files so that we have less to recompile every time CommandLine.h is changed. llvm-svn: 62312
* Delete trailing whitespace.Mikhail Glushenkov2009-01-161-234/+234
| | | | llvm-svn: 62307
* Initial hazard recognizer support in post-pass scheduling. This includesDan Gohman2009-01-161-1/+1
| | | | | | | a new toy hazard recognizier heuristic which attempts to direct the scheduler to avoid clumping large groups of loads or stores too densely. llvm-svn: 62291
* Validate dbg_* intrinsics before lowering them.Devang Patel2009-01-152-10/+10
| | | | llvm-svn: 62286
* Added missing support to widen an operand from a bit convert.Mon P Wang2009-01-152-0/+32
| | | | llvm-svn: 62285
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-152-23/+11
| | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. llvm-svn: 62284
* Add the private linkage.Rafael Espindola2009-01-151-1/+1
| | | | llvm-svn: 62279
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-157-66/+51
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Make getWidenVectorType const; this file was missed in theDan Gohman2009-01-151-1/+1
| | | | | | previous commit. llvm-svn: 62266
* More consts on TargetLowering references.Dan Gohman2009-01-154-10/+9
| | | | llvm-svn: 62262
* Use const with TargetLowering references in a few more places.Dan Gohman2009-01-152-5/+7
| | | | llvm-svn: 62260
* minor refactoring: use a more specific APIGabor Greif2009-01-151-2/+3
| | | | llvm-svn: 62256
* Removoe MachineModuleInfo methods (and related DebugInfoDesc class ↵Devang Patel2009-01-131-1/+1
| | | | | | hierarchy) that were used to handle debug info. llvm-svn: 62199
* Undo previous checkin.Devang Patel2009-01-131-3/+2
| | | | llvm-svn: 62190
* Use dwarf writer to decide whether the module has debug info or not.Devang Patel2009-01-131-2/+3
| | | | llvm-svn: 62184
* The list-td and list-tdrr schedulers don't yet support physregDan Gohman2009-01-132-2/+10
| | | | | | | | | | | scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. llvm-svn: 62177
* When replacing uses and the same node is reachedDuncan Sands2009-01-131-16/+9
| | | | | | | | via two paths, process it once not twice, d'oh! Analysis, testcase and original patch thanks to Mon Ping Wang. llvm-svn: 62169
* Fix some typos. Also, the WidenedVectors mapDuncan Sands2009-01-132-9/+20
| | | | | | was not being cleaned by ExpungeNode. llvm-svn: 62167
* Correct a comment - this is not a sign extension.Duncan Sands2009-01-131-1/+1
| | | | llvm-svn: 62166
* Use DebugInfo interface to lower dbg_* intrinsics.Devang Patel2009-01-136-56/+69
| | | | llvm-svn: 62127
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-124-14/+15
| | | | | | suggested by Chris. llvm-svn: 62099
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-124-61/+84
| | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. llvm-svn: 62074
* CheckForPhysRegDependency should not return copy cost. It's not used. No ↵Evan Cheng2009-01-111-9/+4
| | | | | | functionality change. llvm-svn: 62036
* Duplicated node may produce a non-physical register def.Evan Cheng2009-01-091-3/+5
| | | | llvm-svn: 62015
* Minor debug output tweak.Evan Cheng2009-01-091-2/+2
| | | | llvm-svn: 62005
* Request DwarfWriter. This will be used to handle dbg_* intrinsics.Devang Patel2009-01-092-2/+7
| | | | llvm-svn: 61999
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-091-2/+2
| | | | llvm-svn: 61991
* Remove redundant 'else's. No functionality change.Dan Gohman2009-01-071-7/+6
| | | | llvm-svn: 61891
* Fix a bug in ComputeLinearIndex computation handling multi-levelDan Gohman2009-01-061-1/+3
| | | | | | | | aggregate types. Don't increment the current index after reaching the end of a struct, as it will already be pointing at one-past-the end. This fixes PR3288. llvm-svn: 61828
* Update these argument lists for the isNormalMemoryDan Gohman2009-01-061-3/+6
| | | | | | argument. This doesn't affect current functionality. llvm-svn: 61779
* Use a latency value of 0 for the artificial edges inserted byDan Gohman2009-01-061-1/+1
| | | | | | | | | | | | AddPseudoTwoAddrDeps. This lets the scheduling infrastructure avoid recalculating node heights. In very large testcases this was a major bottleneck. Thanks to Roman Levenstein for finding this! As a side effect, fold-pcmpeqd-0.ll is now scheduled better and it no longer requires spilling on x86-32. llvm-svn: 61778
* TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need itsDan Gohman2009-01-051-2/+0
| | | | | | | own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END, as long as it takes care to round up when needed. llvm-svn: 61733
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-052-3/+0
| | | | llvm-svn: 61715
* squash warnings.Devang Patel2009-01-051-0/+1
| | | | llvm-svn: 61707
* Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.Dan Gohman2009-01-031-0/+2
| | | | llvm-svn: 61613
* CommuteNodesToReducePressure() is now removed.Dan Gohman2009-01-031-1/+0
| | | | llvm-svn: 61612
* Remove the code from the scheduler that commuted two-addressDan Gohman2009-01-032-71/+0
| | | | | | | | | | | | | | instructions to avoid copies, because TwoAddressInstructionPass also does this optimization. The scheduler's version didn't account for live-out values, which resulted in spurious commutes and missed opportunities. Now, TwoAddressInstructionPass handles all the opportunities, instead of just those that the scheduler missed. The result is usually the same, though there are occasional trivial differences resulting from the avoidance of spurious commutes. llvm-svn: 61611
* Factorize (and generalize) the code promoting SELECTDuncan Sands2009-01-013-152/+105
| | | | | | | and BRCOND conditions. Reorder a few methods while there. llvm-svn: 61547
* Remove trailing spaces.Duncan Sands2009-01-012-33/+33
| | | | llvm-svn: 61545
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-017-103/+130
| | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
* Teach LeaglizeDAG that i64 mul can be a libcall.Scott Michel2008-12-291-0/+2
| | | | llvm-svn: 61463
* Change comments so everybody can understand them, hopefully.Dale Johannesen2008-12-231-2/+2
| | | | llvm-svn: 61405
* Add another permutation where we should get rid of a-a.Dale Johannesen2008-12-231-4/+11
| | | | llvm-svn: 61401
* Restore debug printingAnton Korobeynikov2008-12-231-23/+26
| | | | llvm-svn: 61398
* Sometimes APInt syntax is really ugly... :(Anton Korobeynikov2008-12-231-10/+21
| | | | llvm-svn: 61397
* Indent stuff properlyAnton Korobeynikov2008-12-231-25/+25
| | | | llvm-svn: 61396
* Initial checkin of APInt'ififcation of switch loweringAnton Korobeynikov2008-12-232-127/+126
| | | | llvm-svn: 61395
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-234-536/+138
| | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. llvm-svn: 61389
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