summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Instead of enumerating each opcode that isn't handled thatDan Gohman2008-05-061-11/+1
| | | | | | | ComputeMaskedBits handles, just use a 'default:'. This avoids TargetLowering's list getting out of date with SelectionDAG's. llvm-svn: 50693
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-051-1/+1
| | | | llvm-svn: 50663
* typoChris Lattner2008-04-271-1/+1
| | | | llvm-svn: 50316
* Implement a signficant optimization for inline asm:Chris Lattner2008-04-271-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
* Move a bunch of inline asm code out of line.Chris Lattner2008-04-271-0/+97
| | | | llvm-svn: 50313
* A few inline asm cleanups:Chris Lattner2008-04-261-8/+6
| | | | | | | | | - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. llvm-svn: 50312
* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-54/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Prefer to expand mask for xor to -1, so we have a chance to turn it into a not.Torok Edwin2008-04-061-4/+19
| | | | | | | If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
* More APInt-ification.Dan Gohman2008-03-131-1/+1
| | | | llvm-svn: 48344
* Use the correct value for InSignBit.Dan Gohman2008-03-111-1/+1
| | | | llvm-svn: 48245
* Implement more support for fp-to-i128 and i128-to-fp conversions. Dan Gohman2008-03-101-0/+8
| | | | llvm-svn: 48189
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-0/+3
| | | | llvm-svn: 48169
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-101-1/+8
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Codegen support for i128 SINT_TO_FP.Dan Gohman2008-03-051-0/+4
| | | | llvm-svn: 47928
* Yet more APInt-ification.Dan Gohman2008-03-031-9/+6
| | | | llvm-svn: 47867
* More APInt-ification.Dan Gohman2008-03-031-16/+19
| | | | llvm-svn: 47866
* Interface of getByValTypeAlignment differed betweenDale Johannesen2008-02-281-2/+3
| | | | | | | | generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-0/+2
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman2008-02-271-136/+141
| | | | | | | | Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-1/+1
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Refactor inline asm constraint matching code out of SDIsel into TargetLowering.Evan Cheng2008-02-261-2/+2
| | | | llvm-svn: 47587
* Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman2008-02-251-8/+16
| | | | | | a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-141-2/+2
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-141-0/+7
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-131-3/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-131-3/+3
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+3
| | | | llvm-svn: 46930
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Handle 'X' constraint in asm's better.Dale Johannesen2008-01-291-0/+13
| | | | llvm-svn: 46485
* Forgot these.Evan Cheng2008-01-241-0/+6
| | | | llvm-svn: 46292
* remove extraneous &'s.Chris Lattner2008-01-181-2/+2
| | | | llvm-svn: 46171
* This commit changes:Chris Lattner2008-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* Add support for targets that have a legal ISD::TRAP.Chris Lattner2008-01-151-0/+3
| | | | llvm-svn: 46014
* Output sinl for a long double FSIN node, not sin.Duncan Sands2008-01-101-2/+9
| | | | | | | | Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
* fix typo duncan noticed!Chris Lattner2007-12-301-1/+1
| | | | llvm-svn: 45459
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Fold comparisons against a constant nan, and optimize ORD/UNORD Chris Lattner2007-12-291-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
* initial code for forming an FGETSIGN node. This is disabled untilChris Lattner2007-12-221-0/+26
| | | | | | legalizer support goes in. llvm-svn: 45323
* Add a new FGETSIGN operation, which defaults to expand on allChris Lattner2007-12-221-1/+5
| | | | | | targets. llvm-svn: 45320
* Support returning non-power-of-2 vectors to unblock some workNate Begeman2007-11-271-0/+7
| | | | llvm-svn: 44371
* Much improved pic jumptable codegen:Evan Cheng2007-11-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Then: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry imull $4, %ecx, %ecx leal LJTI1_0-"L1$pb"(%eax), %edx addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx jmpl *%edx .align 2 .set L1_0_set_3,LBB1_3-LJTI1_0 .set L1_0_set_2,LBB1_2-LJTI1_0 .set L1_0_set_5,LBB1_5-LJTI1_0 .set L1_0_set_4,LBB1_4-LJTI1_0 LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 Now: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax jmpl *%eax .align 2 .set L1_0_set_3,LBB1_3-"L1$pb" .set L1_0_set_2,LBB1_2-"L1$pb" .set L1_0_set_5,LBB1_5-"L1$pb" .set L1_0_set_4,LBB1_4-"L1$pb" LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 llvm-svn: 43924
* Didn't mean to check these in.Evan Cheng2007-11-091-7/+0
| | | | llvm-svn: 43923
* Bug fix. Passive nodes are not in SUnitMap.Evan Cheng2007-11-091-0/+7
| | | | llvm-svn: 43922
* Move the LowerMEMCPY and LowerMEMCPYCall to a common place.Rafael Espindola2007-11-051-0/+55
| | | | | | Thanks for the suggestions Bill :-) llvm-svn: 43742
* Make labels work in asm blocks; allow labels asDale Johannesen2007-11-051-2/+7
| | | | | | | parameters. Rename ValueRefList to ParamList in AsmParser, since its only use is for parameters. llvm-svn: 43734
* Add runtime library names for pow.Dan Gohman2007-10-111-0/+4
| | | | llvm-svn: 42880
* Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman2007-10-081-8/+20
| | | | | | | | use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
* First round of ppc long double. call/return andDale Johannesen2007-10-051-6/+24
| | | | | | | | | basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
* Add sqrt and powi intrinsics for long double.Dale Johannesen2007-09-281-0/+2
| | | | llvm-svn: 42423
* Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) andDan Gohman2007-09-251-0/+5
| | | | | | | the check to see if the assembler supports .loc from X86TargetLowering into the superclass TargetLowering. llvm-svn: 42297
OpenPOWER on IntegriCloud