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* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-36/+36
| | | | | | Node to reflect semantics llvm-svn: 55504
* Add libcalls for the new rounding opcodes.Dan Gohman2008-08-211-0/+20
| | | | llvm-svn: 55133
* Add the remaining fp_round libcalls:Bruno Cardoso Lopes2008-08-071-2/+15
| | | | | | | | | | | | | FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-54/+54
| | | | llvm-svn: 54128
* Factorize some code for determining which libcall to use.Duncan Sands2008-07-171-0/+158
| | | | llvm-svn: 53713
* It is pointless to turn a UINT_TO_FP into anDuncan Sands2008-07-111-0/+8
| | | | | | | | | SINT_TO_FP libcall plus additional operations: it might as well be a direct UINT_TO_FP libcall. So only turn it into an SINT_TO_FP if the target has special handling for SINT_TO_FP. llvm-svn: 53461
* Add two missing SINT_TO_FP libcalls.Duncan Sands2008-07-111-0/+2
| | | | llvm-svn: 53460
* Add support for 128 bit shifts and 32 bit shiftsDuncan Sands2008-07-111-0/+3
| | | | | | on 16 bit machines. llvm-svn: 53458
* Add support for 128 bit multiplicative operations.Duncan Sands2008-07-101-0/+5
| | | | | | | | | Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
* Add a mysteriously missing libcall, FPTOSINT_F80_I32.Duncan Sands2008-07-101-0/+1
| | | | | | | Be nice to 16 bit machines by supporting FP_TO_XINT expansion for these. llvm-svn: 53407
* Add support for expanding PPC 128 bit floats.Duncan Sands2008-06-251-0/+2
| | | | | | | | | | | | | | | | | | | | For this it is convenient to permit floats to be used with EXTRACT_ELEMENT, so I tweaked things to allow that. I also added libcalls for ppcf128 to i32 forms of FP_TO_XINT, since they exist in libgcc and this case can certainly occur (and does occur in the testsuite) - before the i64 libcall was being used. Also, the XINT_TO_FP result seemed to be wrong when the argument is an i128: the wrong fudge factor was added (the i32 and i64 cases were handled directly, but the i128 code fell through to some generic softening code which seemed to think it was i64 to f32!). So I fixed it by adding a fudge factor that I found in my breakfast cereal. llvm-svn: 52739
* Teach isGAPlusOffset to respect a GlobalAddressSDNode's offsetDan Gohman2008-06-091-1/+3
| | | | | | value, which is something that apparently isn't used much. llvm-svn: 52158
* Various tweaks related to apint codegen. No functionalityDuncan Sands2008-06-091-1/+1
| | | | | | change for non-funky-sized integers. llvm-svn: 52151
* Remove comparison methods for MVT. The main causeDuncan Sands2008-06-081-1/+1
| | | | | | | | | | | of apint codegen failure is the DAG combiner doing the wrong thing because it was comparing MVT's using < rather than comparing the number of bits. Removing the < method makes this mistake impossible to commit. Instead, add helper methods for comparing bits and use them. llvm-svn: 52098
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-73/+76
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Xform bitconvert(build_pair(load a, load b)) to a single load if the load ↵Evan Cheng2008-05-121-1/+1
| | | | | | locations are at the right offset from each other. llvm-svn: 51008
* Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can ↵Evan Cheng2008-05-121-0/+68
| | | | | | make use of it. llvm-svn: 50991
* Instead of enumerating each opcode that isn't handled thatDan Gohman2008-05-061-11/+1
| | | | | | | ComputeMaskedBits handles, just use a 'default:'. This avoids TargetLowering's list getting out of date with SelectionDAG's. llvm-svn: 50693
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-051-1/+1
| | | | llvm-svn: 50663
* typoChris Lattner2008-04-271-1/+1
| | | | llvm-svn: 50316
* Implement a signficant optimization for inline asm:Chris Lattner2008-04-271-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
* Move a bunch of inline asm code out of line.Chris Lattner2008-04-271-0/+97
| | | | llvm-svn: 50313
* A few inline asm cleanups:Chris Lattner2008-04-261-8/+6
| | | | | | | | | - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. llvm-svn: 50312
* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-54/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Prefer to expand mask for xor to -1, so we have a chance to turn it into a not.Torok Edwin2008-04-061-4/+19
| | | | | | | If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
* More APInt-ification.Dan Gohman2008-03-131-1/+1
| | | | llvm-svn: 48344
* Use the correct value for InSignBit.Dan Gohman2008-03-111-1/+1
| | | | llvm-svn: 48245
* Implement more support for fp-to-i128 and i128-to-fp conversions. Dan Gohman2008-03-101-0/+8
| | | | llvm-svn: 48189
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-0/+3
| | | | llvm-svn: 48169
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-101-1/+8
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Codegen support for i128 SINT_TO_FP.Dan Gohman2008-03-051-0/+4
| | | | llvm-svn: 47928
* Yet more APInt-ification.Dan Gohman2008-03-031-9/+6
| | | | llvm-svn: 47867
* More APInt-ification.Dan Gohman2008-03-031-16/+19
| | | | llvm-svn: 47866
* Interface of getByValTypeAlignment differed betweenDale Johannesen2008-02-281-2/+3
| | | | | | | | generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-0/+2
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman2008-02-271-136/+141
| | | | | | | | Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-1/+1
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Refactor inline asm constraint matching code out of SDIsel into TargetLowering.Evan Cheng2008-02-261-2/+2
| | | | llvm-svn: 47587
* Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman2008-02-251-8/+16
| | | | | | a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-141-2/+2
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-141-0/+7
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-131-3/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-131-3/+3
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+3
| | | | llvm-svn: 46930
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Handle 'X' constraint in asm's better.Dale Johannesen2008-01-291-0/+13
| | | | llvm-svn: 46485
* Forgot these.Evan Cheng2008-01-241-0/+6
| | | | llvm-svn: 46292
* remove extraneous &'s.Chris Lattner2008-01-181-2/+2
| | | | llvm-svn: 46171
* This commit changes:Chris Lattner2008-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* Add support for targets that have a legal ISD::TRAP.Chris Lattner2008-01-151-0/+3
| | | | llvm-svn: 46014
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