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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-0/+36
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-5/+4
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* sink a call into its only use.Chris Lattner2011-04-141-2/+1
| | | | llvm-svn: 129503
* During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson2011-04-131-1/+8
| | | | | | where the RHS is of the legal type for the new operation. llvm-svn: 129484
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-011-0/+13
| | | | | | rdar://8911343 llvm-svn: 128696
* BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer2011-03-171-9/+22
| | | | | | | | | | | | | | | | | | | | | | | multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-251-11/+15
| | | | | | the type of the LHS. llvm-svn: 126518
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-131-1/+2
| | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
* Fix an off-by-one error in ctpop combining.Benjamin Kramer2011-01-171-1/+1
| | | | llvm-svn: 123664
* Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0.Benjamin Kramer2011-01-171-0/+24
| | | | | | | | | This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. llvm-svn: 123621
* Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen2011-01-101-1/+2
| | | | | | | | | | | There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. llvm-svn: 123191
* Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng2011-01-061-0/+2
| | | | | | | etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952
* Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky2010-12-191-0/+1
| | | | llvm-svn: 122193
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-20/+16
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* add TLI support indicating that jumps are more expensive than logical operationsChris Lattner2010-11-301-0/+1
| | | | | | and use this to disable a specific optimization. Patch by Micah Villmow! llvm-svn: 120435
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-172/+172
| | | | llvm-svn: 119990
* Fix an inline asm pasto from 117667; was preventingDale Johannesen2010-11-091-1/+2
| | | | | | {i64, i64} from matching i128. llvm-svn: 118465
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-44/+72
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Remove Synthesizable from the Type system; as MMX vectorDale Johannesen2010-10-201-1/+1
| | | | | | | types are no longer Legal on X86, we don't need it. No functional change. 8499854. llvm-svn: 116947
* Fixed pr20314-2.c failure, added E, F, p constraint letters.John Thompson2010-09-211-6/+17
| | | | llvm-svn: 114490
* continue MachinePointerInfo'izing, eliminating use of one of the oldChris Lattner2010-09-211-2/+1
| | | | | | getLoad overloads. llvm-svn: 114443
* Silence more warnings. Two more unused variables.Eric Christopher2010-09-131-2/+0
| | | | llvm-svn: 113771
* Added skeleton for inline asm multiple alternative constraint support.John Thompson2010-09-131-0/+220
| | | | llvm-svn: 113766
* remove some llvmcontext arguments that are now dead post-refactoring.Chris Lattner2010-08-251-1/+1
| | | | llvm-svn: 112104
* Change handling of illegal vector types to widen when possible instead of Chris Lattner2010-08-251-33/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
* PR7586: Make sure we don't claim that unknown bits are actually known in theEli Friedman2010-08-021-3/+2
| | | | | | ISD::AND case of TargetLowering::SimplifyDemandedBits. llvm-svn: 110019
* Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctlyEli Friedman2010-07-301-6/+3
| | | | | | | check the range of the constant when optimizing a comparison between a constant and a sign_extend_inreg node. llvm-svn: 109854
* Use the proper type for shift counts. This fixes a bootstrap error.Dan Gohman2010-07-231-1/+4
| | | | llvm-svn: 109265
* DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bitsDan Gohman2010-07-231-1/+21
| | | | | | are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
* Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng2010-07-211-7/+13
| | | | llvm-svn: 108991
* ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng2010-07-191-6/+7
| | | | | | its scalar floating point registers alias its vector registers. llvm-svn: 108761
* Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng2010-07-191-0/+52
| | | | | | | | for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
* Fix crash reported in PR7653.Devang Patel2010-07-151-1/+1
| | | | llvm-svn: 108441
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-0/+1
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-0/+60
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-0/+60
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-60/+0
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Add X86FastISel support for return statements. This entails refactoringDan Gohman2010-07-071-0/+60
| | | | | | | a bunch of stuff, to allow the target-independent calling convention logic to be employed. llvm-svn: 107800
* Propagate debug loc.Devang Patel2010-07-061-1/+2
| | | | llvm-svn: 107710
* more tidying.Chris Lattner2010-07-051-8/+4
| | | | llvm-svn: 107615
* random tidyingChris Lattner2010-07-051-35/+35
| | | | llvm-svn: 107612
* In asm's, output operands with matching input constraintsDale Johannesen2010-06-281-2/+7
| | | | | | | | have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-2/+0
| | | | llvm-svn: 106901
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-251-5/+3
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-241-4/+4
| | | | llvm-svn: 106746
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar2010-06-231-4/+4
| | | | | | DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. llvm-svn: 106634
* Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach2010-06-231-0/+1
| | | | | | | | atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. llvm-svn: 106630
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-181-0/+4
| | | | llvm-svn: 106342
* Add Expand-to-libcall support for additional atomics. This covers the usualJim Grosbach2010-06-181-0/+28
| | | | | | | | | | entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
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