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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim2019-08-081-0/+11
* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim2019-08-071-4/+19
* [GISel]: Add GISelKnownBits analysisAditya Nandakumar2019-08-061-0/+6
* [TargetLowering] SimplifyMultipleUseDemandedBits - return UNDEF for undemande...Simon Pilgrim2019-08-061-1/+10
* [TargetLowering][X86] Teach SimplifyDemandedVectorElts to replace the base ve...Craig Topper2019-08-041-0/+9
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-7/+11
* [TargetLowering] SimplifyMultipleUseDemandedBits - don't assume INSERT_VECTOR...Simon Pilgrim2019-08-021-1/+1
* [TargetLowering] SimplifyMultipleUseDemandedBits - Add ISD::INSERT_VECTOR_ELT...Simon Pilgrim2019-08-011-0/+10
* [TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through s...Simon Pilgrim2019-07-271-2/+59
* [SelectionDAG] Check for any recursion depth greater than or equal to limit i...Simon Pilgrim2019-07-271-2/+2
* [TargetLowering] Add depth limit to SimplifyMultipleUseDemandedBitsSimon Pilgrim2019-07-271-0/+3
* Revert r367091, it caused PR42777.Nico Weber2019-07-261-59/+2
* [TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG supp...Simon Pilgrim2019-07-261-0/+7
* [TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through s...Simon Pilgrim2019-07-261-2/+59
* [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 foldRoman Lebedev2019-07-241-0/+79
* [SDAG] convert (sub x, 1) to (add x, -1) in ctpop expansion; NFCSanjay Patel2019-07-241-3/+3
* [TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.Simon Pilgrim2019-07-231-0/+23
* [TargetLowering] Add SimplifyMultipleUseDemandedBitsSimon Pilgrim2019-07-231-1/+128
* [Codegen][SelectionDAG] X u% C == 0 fold: non-splat vector improvementsRoman Lebedev2019-07-201-35/+132
* [SDAG] commute setcc operands to match a subtractSanjay Patel2019-07-101-0/+11
* [TargetLowering] support BlockAddress as "i" inline asm constraintNick Desaulniers2019-07-101-0/+7
* [TargetLowering] SimplifyDemandedBits - just call computeKnownBits for BUILD_...Simon Pilgrim2019-07-081-23/+3
* [NFC][TargetLowering] Some preparatory cleanups around 'prepareUREMEqFold()' ...Roman Lebedev2019-07-021-17/+18
* [SelectionDAG] Do minnum->minimum at legalization time instead of building timeBenjamin Kramer2019-07-011-0/+11
* [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)Roman Lebedev2019-06-271-0/+109
* Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM cas...Roman Lebedev2019-06-271-107/+0
* [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)Roman Lebedev2019-06-271-0/+107
* [TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.Simon Pilgrim2019-06-271-0/+18
* [TargetLowering] SimplifyDemandedBits - use DemandedElts to better identify p...Simon Pilgrim2019-06-271-11/+21
* [SDAG] expand ctpop != 1Sanjay Patel2019-06-251-11/+11
* [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG supportSimon Pilgrim2019-06-251-2/+18
* [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim2019-06-251-6/+4
* [SDAG] improve expansion of ctpop+setccSanjay Patel2019-06-251-11/+14
* [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EX...Simon Pilgrim2019-06-251-6/+6
* [TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ...Simon Pilgrim2019-06-251-6/+15
* [Codegen] TargetLowering::SimplifySetCC(): omit urem when possibleRoman Lebedev2019-06-251-0/+12
* Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."Craig Topper2019-06-251-26/+20
* [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG supportSimon Pilgrim2019-06-191-11/+12
* [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_...Simon Pilgrim2019-06-191-3/+4
* [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EX...Simon Pilgrim2019-06-191-6/+10
* [TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handlingSimon Pilgrim2019-06-181-2/+8
* [TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_...Simon Pilgrim2019-06-181-24/+16
* [TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+SIGN_EXTEND_VECTOR_...Simon Pilgrim2019-06-181-25/+17
* [TargetLowering] SimplifyDemandedVectorElts - support MUL and ANY_EXTEND_VECT...Simon Pilgrim2019-06-181-0/+9
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-1/+2
* [TargetLowering] Simplify (ctpop x) == 1David Bolvansky2019-06-091-1/+12
* IR: make getParamByValType Just Work. NFC.Tim Northover2019-06-051-1/+3
* [TargetLowering] SimplifyDemandedBits - pull out shift value type. NFCI.Simon Pilgrim2019-06-051-1/+2
* [TargetLowering] SimplifyDemandedBits - don't use OriginalDemanded variables ...Simon Pilgrim2019-06-021-5/+5
* [TargetLowering] SimplifyDemandedVectorElts - use same arg names as SimplifyD...Simon Pilgrim2019-06-021-4/+4
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