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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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* Start eliminating temporary vectors used to create DAG nodes. Instead, passChris Lattner2006-08-081-73/+53
| | | | | | | | | | | | | | | | | | | in the start of an array and a count of operands where applicable. In many cases, the number of operands is known, so this static array can be allocated on the stack, avoiding the heap. In many other cases, a SmallVector can be used, which has the same benefit in the common cases. I updated a lot of code calling getNode that takes a vector, but ran out of time. The rest of the code should be updated, and these methods should be removed. We should also do the same thing to eliminate the methods that take a vector of MVT::ValueTypes. It would be extra nice to convert the dagiselemitter to avoid creating vectors for operands when calling getTargetNode. llvm-svn: 29566
* Work around a GCC 3.3.5 bug noticed by a user.Chris Lattner2006-08-031-1/+1
| | | | llvm-svn: 29490
* Final polish on machine pass registries.Jim Laskey2006-08-021-8/+19
| | | | llvm-svn: 29471
* Now that the ISel is available, it's possible to create a default instructionJim Laskey2006-08-011-17/+22
| | | | | | scheduler creator. llvm-svn: 29452
* 1. Change use of "Cache" to "Default".Jim Laskey2006-08-011-4/+9
| | | | | | | | | | | 2. Added argument to instruction scheduler creators so the creators can do special things. 3. Repaired target hazard code. 4. Misc. More to follow. llvm-svn: 29450
* Introducing plugable register allocators and instruction schedulers.Jim Laskey2006-08-011-66/+31
| | | | llvm-svn: 29434
* PIC jump table entries are always 32-bit even in 64-bit mode.Evan Cheng2006-08-011-4/+11
| | | | llvm-svn: 29422
* Code cleanups, per reviewNate Begeman2006-07-271-2/+0
| | | | llvm-svn: 29347
* Support jump tables when in PIC relocation modelNate Begeman2006-07-271-4/+10
| | | | llvm-svn: 29318
* Mems can be in the output list also. This is the second half of a fix forChris Lattner2006-07-201-1/+2
| | | | | | PR833 llvm-svn: 29224
* Use hidden visibility to make symbols in an anonymous namespace getChris Lattner2006-06-281-1/+2
| | | | | | dropped. This shrinks libllvmgcc.dylib another 67K llvm-svn: 28975
* Consistency. EXTRACT_ELEMENT index operand should have ptr type.Evan Cheng2006-06-151-10/+13
| | | | llvm-svn: 28795
* Make sure to update the CFG correctly if a switch only has a default dest.Chris Lattner2006-06-121-0/+1
| | | | | | This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll llvm-svn: 28755
* Fix X86/inline-asm.ll:test2, a case where an input value was implicitlyChris Lattner2006-06-081-3/+6
| | | | | | truncated. llvm-svn: 28733
* Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causesChris Lattner2006-06-081-6/+13
| | | | | | implement extension of a register. llvm-svn: 28731
* Make CALL node consistent with RET node. Signness of value has type MVT::i32Evan Cheng2006-05-261-5/+5
| | | | | | | instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type for most (if not all) platforms while MVT::i1 is not. llvm-svn: 28511
* Change RET node to include signness information of the return values. e.g.Evan Cheng2006-05-261-1/+5
| | | | | | RET chain, value1, sign1, value2, sign2 llvm-svn: 28509
* CALL node change: now including signness of every argument.Evan Cheng2006-05-251-2/+7
| | | | llvm-svn: 28461
* -enable-unsafe-fp-math implies -enable-finite-only-fp-mathEvan Cheng2006-05-231-2/+1
| | | | llvm-svn: 28437
* Fix missing includeVladimir Prus2006-05-231-0/+1
| | | | llvm-svn: 28435
* Incorrect SETCC CondCode used for FP comparisons.Evan Cheng2006-05-231-9/+20
| | | | llvm-svn: 28433
* Fix the result of the call to use a correct vbitconvert. There is no need toChris Lattner2006-05-171-23/+8
| | | | | | use getPackedTypeBreakdown at all here. llvm-svn: 28365
* Correct a previous patch which broke CodeGen/PowerPC/vec_call.llChris Lattner2006-05-171-18/+5
| | | | llvm-svn: 28364
* Fixed a LowerCallTo and LowerArguments bug. They were introducing illegalEvan Cheng2006-05-171-12/+27
| | | | | | | | VBIT_VECTOR nodes. There were some confusion about the semantics of getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4, and f32. llvm-svn: 28352
* Add support for calls that pass and return legal vectors.Chris Lattner2006-05-161-3/+60
| | | | llvm-svn: 28340
* Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallToChris Lattner2006-05-161-1/+139
| | | | | | produce it. llvm-svn: 28338
* Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,Chris Lattner2006-05-161-2/+4
| | | | | | | it doesn't currently use/maintain the chain properly. Also, make the X86ISelLowering.cpp file 80-col clean. llvm-svn: 28320
* Move function-live-in-handling code from the sdisel code to the scheduler.Chris Lattner2006-05-161-14/+1
| | | | | | | | | This code should be emitted after legalize, so it can't be in sdisel. Note that the EmitFunctionEntryCode hook should be updated to operate on the DAG. The X86 backend is the only one currently using this hook. llvm-svn: 28315
* Revert an un-intended changeEvan Cheng2006-05-131-16/+27
| | | | llvm-svn: 28278
* Remove dead varsChris Lattner2006-05-121-2/+0
| | | | llvm-svn: 28255
* Refactor scheduler code. Move register-reduction list scheduler to aEvan Cheng2006-05-111-25/+20
| | | | | | | separate file. Added an initial implementation of top-down register pressure reduction list scheduler. llvm-svn: 28226
* Make emission of jump tables a bit less conservative; they are now requiredNate Begeman2006-05-081-4/+4
| | | | | | to be only 31.25% dense, rather than 75% dense. llvm-svn: 28165
* When inserting casts, be careful of where we put them. We cannot insertChris Lattner2006-05-061-9/+12
| | | | | | | | a cast immediately before a PHI node. This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll llvm-svn: 28143
* More aggressively sink GEP offsets into loops. For example, before weChris Lattner2006-05-051-56/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generated: movl 8(%esp), %eax movl %eax, %edx addl $4316, %edx cmpb $1, %cl ja LBB1_2 #cond_false LBB1_1: #cond_true movl L_QuantizationTables720$non_lazy_ptr, %ecx movl %ecx, (%edx) movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx movl %edx, 4460(%eax) ret ... Now we generate: movl 8(%esp), %eax cmpb $1, %cl ja LBB1_2 #cond_false LBB1_1: #cond_true movl L_QuantizationTables720$non_lazy_ptr, %ecx movl %ecx, 4316(%eax) movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx movl %ecx, 4460(%eax) ret ... which uses one fewer register. llvm-svn: 28129
* Sink noop copies into the basic block that uses them. This reduces the numberChris Lattner2006-05-051-4/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of cross-block live ranges, and allows the bb-at-a-time selector to always coallesce these away, at isel time. This reduces the load on the coallescer and register allocator. For example on a codec on X86, we went from: 1643 asm-printer - Number of machine instrs printed 419 liveintervals - Number of loads/stores folded into instructions 1144 liveintervals - Number of identity moves eliminated after coalescing 1022 liveintervals - Number of interval joins performed 282 liveintervals - Number of intervals after coalescing 1304 liveintervals - Number of original intervals 86 regalloc - Number of times we had to backtrack 1.90232 regalloc - Ratio of intervals processed over total intervals 40 spiller - Number of values reused 182 spiller - Number of loads added 121 spiller - Number of stores added 132 spiller - Number of register spills 6 twoaddressinstruction - Number of instructions commuted to coalesce 360 twoaddressinstruction - Number of two-address instructions to: 1636 asm-printer - Number of machine instrs printed 403 liveintervals - Number of loads/stores folded into instructions 1155 liveintervals - Number of identity moves eliminated after coalescing 1033 liveintervals - Number of interval joins performed 279 liveintervals - Number of intervals after coalescing 1312 liveintervals - Number of original intervals 76 regalloc - Number of times we had to backtrack 1.88998 regalloc - Ratio of intervals processed over total intervals 1 spiller - Number of copies elided 41 spiller - Number of values reused 191 spiller - Number of loads added 114 spiller - Number of stores added 128 spiller - Number of register spills 4 twoaddressinstruction - Number of instructions commuted to coalesce 356 twoaddressinstruction - Number of two-address instructions On this testcase, this change provides a modest reduction in spill code, regalloc iterations, and total instructions emitted. It increases the number of register coallesces. llvm-svn: 28115
* Finish up the initial jump table implementation by allowing jump tables toNate Begeman2006-05-031-26/+34
| | | | | | | not be 100% dense. Increase the minimum threshold for the number of cases in a switch statement from 4 to 6 in order to create a jump table. llvm-svn: 28079
* Refactor TargetMachine, pushing handling of TargetData into the ↵Owen Anderson2006-05-031-19/+19
| | | | | | | | target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759. llvm-svn: 28074
* Remove the temporary option: -no-isel-fold-inflightEvan Cheng2006-04-281-11/+0
| | | | llvm-svn: 28012
* TargetLowering::LowerArguments should return a VBIT_CONVERT ofEvan Cheng2006-04-281-16/+14
| | | | | | FORMAL_ARGUMENTS SDOperand in the return result vector. llvm-svn: 28009
* Added a temporary option -no-isel-fold-inflight to control whether a "inflight"Evan Cheng2006-04-281-1/+12
| | | | | | node can be folded. llvm-svn: 28003
* Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector usesEvan Cheng2006-04-271-3/+16
| | | | | | (VAND, VADD, etc.). Legalizer will assert otherwise. llvm-svn: 27991
* Don't forget return void.Evan Cheng2006-04-251-0/+3
| | | | llvm-svn: 27974
* Fix the updating of the machine CFG when a PHI node was in a successor ofNate Begeman2006-04-231-5/+10
| | | | | | | the jump table's range check block. This re-enables 100% dense jump tables by default on PPC & x86 llvm-svn: 27952
* Turn of jump tables for a bit, there are still some issues to work out withNate Begeman2006-04-221-1/+1
| | | | | | updating the machine CFG. llvm-svn: 27949
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-6/+138
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrapChris Lattner2006-04-211-2/+5
| | | | | | miscompares). Switch RISC targets to use the list-td scheduler, which isn't. llvm-svn: 27933
* Implement support for the formal_arguments node. To get this, targets ↵Chris Lattner2006-04-121-0/+119
| | | | | | shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload llvm-svn: 27604
* Add code generator support for VSELECTChris Lattner2006-04-081-2/+8
| | | | llvm-svn: 27542
* Codegen shufflevector as VVECTOR_SHUFFLEChris Lattner2006-04-081-1/+13
| | | | llvm-svn: 27529
* Stub out shufflevectorChris Lattner2006-04-081-0/+1
| | | | llvm-svn: 27514
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