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* Add the support in code-gen for the landingpad instruction lowering.Bill Wendling2011-08-171-3/+39
| | | | | | | | | | The landingpad instruction is lowered into the EXCEPTIONADDR and EHSELECTION SDNodes. The information from the landingpad instruction is harvested by the 'AddLandingPadInfo' function. The new EH uses the current EH scheme in the back-end. This will change once we switch over to the new scheme. (Reviewed by Jakob!) llvm-svn: 137880
* Revert patch. Forgot a dependent commit.Bill Wendling2011-08-171-39/+3
| | | | llvm-svn: 137875
* Add the body of 'visitLandingPad'.Bill Wendling2011-08-171-3/+39
| | | | | | | | This generates the SDNodes for the new exception handling scheme. It takes the two values coming from the landingpad instruction and assigns them to the EXCEPTIONADDR and EHSELECTION nodes. llvm-svn: 137873
* Initial commit of the 'landingpad' instruction.Bill Wendling2011-08-121-0/+3
| | | | | | | | | | | | This implements the 'landingpad' instruction. It's used to indicate that a basic block is a landing pad. There are several restrictions on its use (see LangRef.html for more detail). These restrictions allow the exception handling code to gather the information it needs in a much more sane way. This patch has the definition, implementation, C interface, parsing, and bitcode support in it. llvm-svn: 137501
* Do not drop undef debug values. These are used as range termination marker ↵Devang Patel2011-08-031-1/+1
| | | | | | by live debug variable pass. llvm-svn: 136834
* New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman2011-08-031-8/+59
| | | | | | | | platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
* Add the 'resume' instruction for the new EH rewrite.Bill Wendling2011-07-311-0/+4
| | | | | | | | | This adds the 'resume' instruction class, IR parsing, and bitcode reading and writing. The 'resume' instruction resumes propagation of an existing (in-flight) exception whose unwinding was interrupted with a 'landingpad' instruction (to be added later). llvm-svn: 136589
* Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,Bill Wendling2011-07-301-44/+0
| | | | | | | r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444, r136445, r136446, r136253 pending review. llvm-svn: 136556
* Do not lose branch weights when lowering SwitchInst.Jakub Staszak2011-07-291-11/+32
| | | | llvm-svn: 136529
* Remove unneeded const_cast.Jakub Staszak2011-07-291-2/+2
| | | | llvm-svn: 136506
* Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to beEli Friedman2011-07-291-2/+41
| | | | | | | | | working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) llvm-svn: 136457
* Use the pointer type size.Bill Wendling2011-07-291-1/+1
| | | | | | With this, we can now compile a simple EH program. llvm-svn: 136446
* And now something that compiles...Bill Wendling2011-07-291-1/+1
| | | | llvm-svn: 136445
* Make sure to sext or trunc the result from the register.Bill Wendling2011-07-291-2/+2
| | | | llvm-svn: 136444
* Visit the landingpad instruction.Bill Wendling2011-07-281-1/+35
| | | | | | | | | This generates the correct SDNodes for the landingpad instruction. It makes an assumption that the result of the landingpad instruction has at least two values. And that the first value is a pointer to the exception object and the second value is the "selector." llvm-svn: 136430
* LangRef and basic memory-representation/reading/writing for 'cmpxchg' andEli Friedman2011-07-281-0/+6
| | | | | | | | | | | | | | | | | | | | | 'atomicrmw' instructions, which allow representing all the current atomic rmw intrinsics. The allowed operands for these instructions are heavily restricted at the moment; we can probably loosen it a bit, but supporting general first-class types (where it makes sense) might get a bit complicated, given how SelectionDAG works. As an initial cut, these operations do not support specifying an alignment, but it would be possible to add if we think it's useful. Specifying an alignment lower than the natural alignment would be essentially impossible to support on anything other than x86, but specifying a greater alignment would be possible. I can't think of any useful optimizations which would use that information, but maybe someone else has ideas. Optimizer/codegen support coming soon. llvm-svn: 136404
* The personality function should be a Function* and not just a Value*.Bill Wendling2011-07-281-4/+6
| | | | llvm-svn: 136392
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-1/+6
| | | | llvm-svn: 136283
* Merge the contents from exception-handling-rewrite to the mainline.Bill Wendling2011-07-271-0/+8
| | | | | | This adds the new instructions 'landingpad' and 'resume'. llvm-svn: 136253
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-271-1/+2
| | | | | | C++0x. llvm-svn: 136211
* Initial implementation of 'fence' instruction, the new C++0x-style ↵Eli Friedman2011-07-251-0/+4
| | | | | | | | replacement for llvm.memory.barrier. This is just a LangRef entry and reading/writing/memory representation; optimizer+codegen support coming soon. llvm-svn: 136009
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-34/+34
| | | | llvm-svn: 135375
* Check register class matching instead of width of type matchingEric Christopher2011-07-141-4/+6
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-141-1/+9
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
* Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.Jay Foad2011-07-131-2/+2
| | | | llvm-svn: 135040
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+7
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* Apparently we can't expect a BinaryOperator here.Benjamin Kramer2011-07-081-2/+2
| | | | | | Should fix llvm-gcc selfhost. llvm-svn: 134699
* Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer2011-07-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax llvm-svn: 134695
* Introduce "expect" intrinsic instructions.Jakub Staszak2011-07-061-0/+7
| | | | llvm-svn: 134516
* Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-301-101/+0
| | | | | | Fixes rdar://9643582 llvm-svn: 134123
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. llvm-svn: 133902
* When promoting the vector elements in CopyToParts, use vector truncNadav Rotem2011-06-191-11/+3
| | | | | | instead of scalarizing, and doing an element-by-element truncat. llvm-svn: 133382
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-161-11/+32
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-161-9/+16
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+3
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
* Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem2011-06-121-21/+20
| | | | | | | | | Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). llvm-svn: 132892
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-3/+5
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
| | | | llvm-svn: 132559
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-021-1/+1
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-011-0/+6
| | | | | | | | types if the vector type is legal. Fixes rdar://9306086 llvm-svn: 132420
* Preserve debug info during iSel by keeping DanglingDebugInfoMap live until ↵Devang Patel2011-05-231-1/+10
| | | | | | | | end of function. Patch by Micah Villmow llvm-svn: 131908
* Eliminate some temporary variables, and don't call getByValTypeAlignmentChris Lattner2011-05-221-6/+8
| | | | | | when we're just going to throw the result away. No functionality change. llvm-svn: 131880
* Preserve debug info for unused zero extended boolean argument.Devang Patel2011-05-161-6/+27
| | | | | | Radar 9422775. llvm-svn: 131422
* Make codegen able to handle values of empty types. This is one wayRafael Espindola2011-05-131-6/+29
| | | | | | to fix PR9900. I will keep it open until sable is able to comment on it. llvm-svn: 131294
* Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmpBill Wendling2011-05-111-1/+1
| | | | | | | | intrinsic call. This prevents it from being reordered so that it appears *before* the setjmp intrinsic (thus making it completely useless). <rdar://problem/9409683> llvm-svn: 131174
* Disable my little CopyToReg argument hack with fast-isel. ↵Eli Friedman2011-05-101-2/+3
| | | | | | rdar://problem/9413587 . llvm-svn: 131156
* Look through struct wrapped types for inline asm statments.Eric Christopher2011-05-091-0/+6
| | | | | | Patch by Evan Cheng. llvm-svn: 131093
* 80 col violations.Evan Cheng2011-05-061-3/+7
| | | | llvm-svn: 131015
* Avoid extra vreg copies for arguments passed in registers. Specifically, ↵Eli Friedman2011-05-051-12/+44
| | | | | | this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . llvm-svn: 130928
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