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* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-688/+0
| | | | | | | | into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-4/+3
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-5/+8
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* change selectiondag to add the sign extended versions of immediate operandsChris Lattner2009-09-081-1/+1
| | | | | | | | to instructions instead of zero extended ones. This makes the asmprinter print signed values more consistently. This apparently only really affects the X86 backend. llvm-svn: 81265
* Remove Offset from ExternalSybmol MachineOperands, this is unused (and at ↵Daniel Dunbar2009-09-011-1/+1
| | | | | | least partly unsupported, in X86 encoding at least). llvm-svn: 80726
* Be more clever about regclasses in ScheduleDAGSDNodes::EmitCopyFromReg.Jakob Stoklund Olesen2009-08-161-5/+5
| | | | | | | | If two uses of a CopyFromReg want different regclasses, first try a common sub-class, then fall back on the copy emitted in AddRegisterOperand. There is no need for an assert here. The cross-class joiner usually cleans up nicely. llvm-svn: 79193
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-6/+6
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-9/+9
| | | | | | own struct type. llvm-svn: 78610
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-301-0/+1
| | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582
* inline the global 'getInstrOperandRegClass' function into its callersChris Lattner2009-07-291-7/+8
| | | | | | now that TargetOperandInfo does the heavy lifting. llvm-svn: 77508
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-4/+4
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-4/+5
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Fix up support for OptionalDefOperand when it defaults to an actual register ↵Evan Cheng2009-07-111-4/+16
| | | | | | def. I need this to get ready for major Thumb1 surgery. llvm-svn: 75328
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-1/+1
| | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
* propagate target operand flags from dag nodes into MachineOperands.Chris Lattner2009-06-261-4/+8
| | | | llvm-svn: 74273
* fit in 80 colsChris Lattner2009-06-261-5/+4
| | | | llvm-svn: 74270
* Silence Release-Asserts warnings.Daniel Dunbar2009-05-181-0/+4
| | | | llvm-svn: 72011
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-091-1/+1
| | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. llvm-svn: 71349
* Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.Evan Cheng2009-05-051-14/+0
| | | | llvm-svn: 70950
* Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a ↵Jakob Stoklund Olesen2009-04-281-14/+3
| | | | | | | | | | TargetRegisterClass method. Also make the method non-asserting. It will return NULL when given an invalid subreg index. The method is needed by an upcoming patch. llvm-svn: 70296
* Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman2009-04-201-25/+0
| | | | | | | This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. llvm-svn: 69635
* When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REGDan Gohman2009-04-141-20/+19
| | | | | | | | | | | | operator is used by a CopyToReg to export the value to a different block, don't reuse the CopyToReg's register for the subreg operation result if the register isn't precisely the right class for the subreg operation. Also, rename the h-registers.ll test, now that there are more than one. llvm-svn: 69087
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-12/+11
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-75/+157
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Now that register classes have names, include the name in debug output.Dan Gohman2009-04-101-2/+4
| | | | llvm-svn: 68786
* For inline asm output operand that matches an input. Encode the input ↵Evan Cheng2009-03-201-1/+1
| | | | | | operand index in the high bits. llvm-svn: 67387
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-7/+9
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* If the target cannot issue a copy for the given source and dest registers, ↵Evan Cheng2009-02-091-5/+10
| | | | | | abort instead of silently continue. llvm-svn: 64184
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-8/+6
| | | | llvm-svn: 63938
* Move ScheduleDAGSDNodes.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | that previously included this header should include SchedulerRegistry.h instead. llvm-svn: 63937
* Propagate debug loc info during SDNode -> machine instr creation.Bill Wendling2009-02-031-6/+9
| | | | llvm-svn: 63585
* Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng2009-01-221-33/+2
| | | | | | SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. llvm-svn: 62762
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-8/+9
| | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. llvm-svn: 62366
* CreateVirtualRegisters does trivial copy coalescing. If a node def is used ↵Evan Cheng2009-01-161-56/+62
| | | | | | by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. llvm-svn: 62356
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-4/+4
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-1/+1
| | | | | | suggested by Chris. llvm-svn: 62099
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-121-4/+7
| | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. llvm-svn: 62074
* Duplicated node may produce a non-physical register def.Evan Cheng2009-01-091-3/+5
| | | | llvm-svn: 62015
* Remove the code from the scheduler that commuted two-addressDan Gohman2009-01-031-17/+0
| | | | | | | | | | | | | | instructions to avoid copies, because TwoAddressInstructionPass also does this optimization. The scheduler's version didn't account for live-out values, which resulted in spurious commutes and missed opportunities. Now, TwoAddressInstructionPass handles all the opportunities, instead of just those that the scheduler missed. The result is usually the same, though there are occasional trivial differences resulting from the avoidance of spurious commutes. llvm-svn: 61611
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-0/+661
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. llvm-svn: 59676
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