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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
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* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-0/+6
| | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing llvm-svn: 129100
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-2/+30
| | | | | | | | | | | | | | | precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. llvm-svn: 124853
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-0/+1
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* Code refactoring, no functionality changes.Evan Cheng2010-06-101-1/+4
| | | | llvm-svn: 105775
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-201-12/+1
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-0/+9
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+1
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Three changes:Chris Lattner2010-04-071-1/+2
| | | | | | | | | | | | | | | 1. Introduce some enums and accessors in the InlineAsm class that eliminate a ton of magic numbers when handling inline asm SDNode. 2. Add a new MDNodeSDNode selection dag node type that holds a MDNode (shocking!) 3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc metadata, propagating it to the instruction emitter, which drops it. No functionality change. llvm-svn: 100605
* Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ↵Evan Cheng2010-01-221-0/+4
| | | | | | improve cache locality. This is controlled by -cluster-loads for now. llvm-svn: 94148
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85556
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-60/+0
| | | | | | | | into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-091-1/+1
| | | | | | it isn't needed in the ScheduleDAGSDNodes schedulers. llvm-svn: 83691
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-8/+3
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-2/+4
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-2/+2
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-0/+13
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-0/+7
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Delete an unused member function.Dan Gohman2009-02-061-2/+0
| | | | llvm-svn: 63941
* Move ScheduleDAGSDNodes.h to be a private header. Front-endsDan Gohman2009-02-061-0/+161
that previously included this header should include SchedulerRegistry.h instead. llvm-svn: 63937
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