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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
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* Use the new PriorityQueue in ScheduleDAGList too, which alsoDan Gohman2008-06-231-19/+3
| | | | | | needs arbitrary-element removal. llvm-svn: 52654
* Remove ScheduleDAG's SUnitMap altogether. Instead, use SDNode's NodeIdDan Gohman2008-06-211-3/+2
| | | | | | | field, which is otherwise unused after instruction selection, as an index into the SUnit array. llvm-svn: 52583
* Change ScheduleDAG's SUnitMap from DenseMap<SDNode*, vector<SUnit*> >Dan Gohman2008-06-211-1/+2
| | | | | | | | to DenseMap<SDNode*, SUnit*>, and adjust the way cloned SUnit nodes are handled so that only the original node needs to be in the map. This speeds up llc on 447.dealII.llvm.bc by about 2%. llvm-svn: 52576
* Treat EntryToken nodes as "passive" so that they aren't added to theDan Gohman2008-04-151-6/+1
| | | | | | | | | | | | | | | | | ScheduleDAG; they don't correspond to any actual instructions so they don't need to be scheduled. This fixes a bug where the EntryToken was being scheduled multiple times in some cases, though it ended up not causing any trouble because EntryToken doesn't expand into anything. With this fixed the schedulers reliably schedule the expected number of units, so we can check this with an assertion. This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it ends up getting scheduled differently in a trivial way, though it was enough to fool the prcontext+grep that the test does. llvm-svn: 49701
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* Use empty() instead of comparing size() with zero.Dan Gohman2008-01-291-2/+2
| | | | llvm-svn: 46514
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-1/+0
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Make CalcLatency() non-recursive.Evan Cheng2007-10-151-9/+44
| | | | llvm-svn: 43017
* Trim some unneeded fields.Evan Cheng2007-09-281-7/+4
| | | | llvm-svn: 42442
* Added major new capabilities to scheduler (only BURR for now) to support ↵Evan Cheng2007-09-251-19/+33
| | | | | | physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. llvm-svn: 42284
* Use struct SDep instead of std::pair for SUnit pred and succ lists. First stepEvan Cheng2007-09-191-7/+7
| | | | | | in tracking physical register output dependencies. llvm-svn: 42125
* Skeleton of post-RA scheduler; doesn't do anything yet.Dale Johannesen2007-07-131-1/+1
| | | | | | | Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816
* switch the sched unit map over to use a DenseMap instead of std::map. ThisChris Lattner2007-02-031-1/+1
| | | | | | speeds up isel as a whole time by 2.6%. llvm-svn: 33810
* Eliminate static ctors from StatisticsChris Lattner2006-12-191-4/+2
| | | | llvm-svn: 32698
* Removing even more <iostream> includes.Bill Wendling2006-12-071-9/+8
| | | | llvm-svn: 32320
* Detemplatize the Statistic class. The only type it is instantiated withChris Lattner2006-12-061-2/+2
| | | | | | is 'unsigned'. llvm-svn: 32279
* Changes to use operand constraints to process two-address instructions.Evan Cheng2006-11-041-2/+3
| | | | llvm-svn: 31453
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | llvm-svn: 29911
* switch the SUnit pred/succ sets from being std::sets to being smallvectors.Chris Lattner2006-08-171-20/+24
| | | | | | | | This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms, a 33% speedup. llvm-svn: 29743
* Final polish on machine pass registries.Jim Laskey2006-08-021-1/+1
| | | | llvm-svn: 29471
* 1. Change use of "Cache" to "Default".Jim Laskey2006-08-011-2/+4
| | | | | | | | | | | 2. Added argument to instruction scheduler creators so the creators can do special things. 3. Repaired target hazard code. 4. Misc. More to follow. llvm-svn: 29450
* Introducing plugable register allocators and instruction schedulers.Jim Laskey2006-08-011-7/+12
| | | | llvm-svn: 29434
* Reduce number of exported symbolsAndrew Lenharth2006-07-201-2/+2
| | | | llvm-svn: 29220
* Shave another 27K off libllvmgcc.dylib with visibility hiddenChris Lattner2006-06-281-1/+2
| | | | llvm-svn: 28973
* When a priority_queue is empty, the behavior of top() operator isEvan Cheng2006-05-301-0/+1
| | | | | | non-deterministic. Returns NULL when it's empty! llvm-svn: 28560
* Refactor a bunch of includes so that TargetMachine.h doesn't have to includeOwen Anderson2006-05-121-0/+1
| | | | | | | TargetData.h. This should make recompiles a bit faster with my current TargetData tinkering. llvm-svn: 28238
* Refactor scheduler code. Move register-reduction list scheduler to aEvan Cheng2006-05-111-907/+20
| | | | | | | separate file. Added an initial implementation of top-down register pressure reduction list scheduler. llvm-svn: 28226
* Templatify RegReductionPriorityQueueEvan Cheng2006-05-101-7/+12
| | | | llvm-svn: 28212
* Add pseudo dependency to force a def&use operand to be scheduled last (unlessEvan Cheng2006-05-091-17/+108
| | | | | | | the distance between the def and another use is much longer). This is under option control for now "-sched-lower-defnuse". llvm-svn: 28201
* Fix VC++ compilation error.Jeff Cohen2006-05-051-1/+1
| | | | llvm-svn: 28117
* Initial support for register pressure aware scheduling. The register reductionEvan Cheng2006-05-041-50/+238
| | | | | | | | | | scheduler can go into a "vertical mode" (i.e. traversing up the two-address chain, etc.) when the register pressure is low. This does seem to reduce the number of spills in the cases I've looked at. But with x86, it's no guarantee the performance of the code improves. It can be turned on with -sched-vertically option. llvm-svn: 28108
* Bottom up register pressure reduction work: clean up some hacks and enhancedEvan Cheng2006-05-031-75/+72
| | | | | | | the heuristic to further reduce spills for several test cases. (Note, it may not necessarily translate to runtime win!) llvm-svn: 28076
* Dis-favor stores moreEvan Cheng2006-05-011-2/+2
| | | | llvm-svn: 28035
* Bottom up register-pressure reduction scheduler now pushes store operationsEvan Cheng2006-05-011-17/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. llvm-svn: 28033
* Didn't mean ScheduleDAGList.cpp to make the last checkin.Evan Cheng2006-05-011-33/+17
| | | | llvm-svn: 28030
* Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng2006-05-011-17/+33
| | | | | | performance regressions. llvm-svn: 28029
* Don't advance the hazard recognizer when there are no hazards and no ↵Chris Lattner2006-03-121-25/+40
| | | | | | | | | | | instructions to be emitted. Don't add one to the latency of a completed instruction if the latency of the op is 0. llvm-svn: 26718
* Chain operands aren't real uses: they don't require the full latency of theChris Lattner2006-03-121-4/+10
| | | | | | predecessor to finish before they can start. llvm-svn: 26717
* As a pending queue data structure to keep track of instructions whoseChris Lattner2006-03-121-36/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | operands have all issued, but whose results are not yet available. This allows us to compile: int G; int test(int A, int B, int* P) { return (G+A)*(B+1); } to: _test: lis r2, ha16(L_G$non_lazy_ptr) addi r4, r4, 1 lwz r2, lo16(L_G$non_lazy_ptr)(r2) lwz r2, 0(r2) add r2, r2, r3 mullw r3, r2, r4 blr instead of this, which has a stall between the lis/lwz: _test: lis r2, ha16(L_G$non_lazy_ptr) lwz r2, lo16(L_G$non_lazy_ptr)(r2) addi r4, r4, 1 lwz r2, 0(r2) add r2, r2, r3 mullw r3, r2, r4 blr llvm-svn: 26716
* rename priorityqueue -> availablequeue. When a node is scheduled, rememberChris Lattner2006-03-111-34/+37
| | | | | | which cycle it lands on. llvm-svn: 26714
* Make CurrCycle a local var instead of an instance varChris Lattner2006-03-111-19/+20
| | | | llvm-svn: 26713
* Move some methods around so that BU specific code is together, TD specific codeChris Lattner2006-03-111-236/+245
| | | | | | is together, and direction independent code is together. llvm-svn: 26712
* merge preds/chainpreds -> preds setChris Lattner2006-03-111-93/+61
| | | | | | | | | merge succs/chainsuccs -> succs set This has no functionality change, simplifies the code, and reduces the size of sunits. llvm-svn: 26711
* Move some simple-sched-specific instance vars to the simple scheduler.Chris Lattner2006-03-101-1/+1
| | | | llvm-svn: 26690
* Make EmitNode take a SDNode instead of a NodeInfo*Chris Lattner2006-03-101-8/+3
| | | | llvm-svn: 26687
* Move the VRBase field from NodeInfo to being a separate, explicit, map.Chris Lattner2006-03-101-2/+3
| | | | llvm-svn: 26686
* no need to build groups anymoreChris Lattner2006-03-101-2/+0
| | | | llvm-svn: 26684
* Create SUnits directly from the SelectionDAG.Chris Lattner2006-03-101-87/+87
| | | | llvm-svn: 26683
* Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchyChris Lattner2006-03-101-0/+5
| | | | llvm-svn: 26682
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