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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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* Separate MachineInstr-emitting routines from actual schedulingDan Gohman2008-09-031-751/+1
| | | | | | routines and move them into a separate file, ScheduleDAGEmit.cpp. llvm-svn: 55699
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-10/+10
| | | | | | Node to reflect semantics llvm-svn: 55504
* Optimize ScheduleDAG's ComputeDepths and ComputeHeights to not needDan Gohman2008-08-271-14/+14
| | | | | | a scratch std::vector. llvm-svn: 55420
* disallow direct access to SDValue::ResNo, provide a getter insteadGabor Greif2008-08-261-7/+7
| | | | llvm-svn: 55394
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-20/+20
| | | | llvm-svn: 54128
* Tidy SDNode::use_iterator, and complete the transition to have itDan Gohman2008-07-271-27/+27
| | | | | | | parallel its analogue, Value::value_use_iterator. The operator* method now returns the user, rather than the use. llvm-svn: 54127
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
* Reapply 53476 and 53480, with a fix so that it properly updatesDan Gohman2008-07-141-3/+8
| | | | | | | the BB member to the current basic block after emitting instructions. llvm-svn: 53567
* Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.Evan Cheng2008-07-121-5/+0
| | | | llvm-svn: 53502
* Fix an obsolete top-level comment.Dan Gohman2008-07-111-3/+2
| | | | llvm-svn: 53481
* Factor out debugging code into the common base class.Dan Gohman2008-07-111-0/+5
| | | | llvm-svn: 53480
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-6/+6
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Make DenseMap's insert return a pair, to more closely resemble std::map.Dan Gohman2008-07-071-7/+11
| | | | llvm-svn: 53177
* Replace a few uses of SelectionDAG::getTargetNode withDan Gohman2008-07-021-32/+2
| | | | | | | | | | | | SelectionDAG::SelectNodeTo in the instruction selector. This updates existing nodes in place instead of creating new ones. Go back to selecting ISD::DBG_LABEL nodes into TargetInstrInfo::DBG_LABEL nodes instead of leaving them unselected, now that SelectNodeTo allows us to update them in place. llvm-svn: 53057
* - Use a faster priority comparison function if -fast.Evan Cheng2008-07-021-134/+139
| | | | | | - Code clean up. llvm-svn: 53010
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-1/+8
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Remove a redundant return.Dan Gohman2008-06-211-2/+0
| | | | llvm-svn: 52585
* Remove ScheduleDAG's SUnitMap altogether. Instead, use SDNode's NodeIdDan Gohman2008-06-211-11/+15
| | | | | | | field, which is otherwise unused after instruction selection, as an index into the SUnit array. llvm-svn: 52583
* Add a priority queue class, which is a wrapper around std::priority_queueDan Gohman2008-06-211-1/+0
| | | | | | | and provides fairly efficient removal of arbitrary elements. Switch ScheduleDAGRRList from std::set to this new priority queue. llvm-svn: 52582
* Change ScheduleDAG's SUnitMap from DenseMap<SDNode*, vector<SUnit*> >Dan Gohman2008-06-211-15/+20
| | | | | | | | to DenseMap<SDNode*, SUnit*>, and adjust the way cloned SUnit nodes are handled so that only the original node needs to be in the map. This speeds up llc on 447.dealII.llvm.bc by about 2%. llvm-svn: 52576
* Clean up some uses of std::distance, now that we have allnodes_size.Dan Gohman2008-06-201-2/+2
| | | | llvm-svn: 52545
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-3/+3
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Use a better idiom to silence compiler warnings.Evan Cheng2008-05-141-20/+5
| | | | llvm-svn: 51131
* Really silence compiler warnings.Evan Cheng2008-05-141-5/+20
| | | | llvm-svn: 51123
* Silence some compiler warnings.Evan Cheng2008-05-141-1/+8
| | | | llvm-svn: 51115
* Switch to using Simplified ConstantFP::get API.Chris Lattner2008-04-201-2/+1
| | | | llvm-svn: 49977
* Ongoing work on improving the instruction selection infrastructure:Roman Levenstein2008-04-161-8/+8
| | | | | | | | | | Rename SDOperandImpl back to SDOperand. Introduce the SDUse class that represents a use of the SDNode referred by an SDOperand. Now it is more similar to Use/Value classes. Patch is approved by Dan Gohman. llvm-svn: 49795
* Treat EntryToken nodes as "passive" so that they aren't added to theDan Gohman2008-04-151-2/+5
| | | | | | | | | | | | | | | | | ScheduleDAG; they don't correspond to any actual instructions so they don't need to be scheduled. This fixes a bug where the EntryToken was being scheduled multiple times in some cases, though it ended up not causing any trouble because EntryToken doesn't expand into anything. With this fixed the schedulers reliably schedule the expected number of units, so we can check this with an assertion. This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it ends up getting scheduled differently in a trivial way, though it was enough to fool the prcontext+grep that the test does. llvm-svn: 49701
* Rename MemOperand to MachineMemOperand. This was suggested byDan Gohman2008-04-071-2/+2
| | | | | | | review feedback from Chris quite a while ago. No functionality change. llvm-svn: 49348
* Re-commit of the r48822, where the infinite looping problem discoveredRoman Levenstein2008-04-071-14/+14
| | | | | | by Dan Gohman is fixed. llvm-svn: 49330
* Start of a series of patches related to implicit_def.Evan Cheng2008-04-031-37/+70
| | | | | | There is no point in creating a long live range defined by an implicit_def. Scheduler now duplicates implicit_def instruction for each of its uses. Therefore, if an implicit_def node has multiple uses, it will become a number of very short live ranges, rather than a long one. This will make coalescer's job easier. llvm-svn: 49164
* Backing out 48222 temporarily.Evan Cheng2008-04-031-13/+13
| | | | llvm-svn: 49124
* Use a linked data structure for the uses lists of an SDNode, just like Roman Levenstein2008-03-261-13/+13
| | | | | | | | | | | | | LLVM Value/Use does and MachineRegisterInfo/MachineOperand does. This allows constant time for all uses list maintenance operations. The idea was suggested by Chris. Reviewed by Evan and Dan. Patch is tested and approved by Dan. On normal use-cases compilation speed is not affected. On very big basic blocks there are compilation speedups in the range of 15-20% or even better. llvm-svn: 48822
* A quick nm audit turned up several fixed tables and objects that wereDan Gohman2008-03-251-4/+4
| | | | | | | marked read-write. Use const so that they can be allocated in a read-only segment. llvm-svn: 48800
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-47/+28
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-3/+8
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Livein copy scheduling fixes: do not coalesce physical register copies, ↵Evan Cheng2008-03-141-112/+42
| | | | | | correctly determine the safe location to insert the copies. llvm-svn: 48348
* Experimental scheduler change to schedule / coalesce the copies added for ↵Evan Cheng2008-03-121-23/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1028<def> = MOV32rr %EAX %reg1029<def> = MOV32rr %EDX %reg1030<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0] %reg1025<def> = MOV32rr %reg1029 %reg1026<def> = MOV32rr %reg1030 %reg1024<def> = MOV32rr %reg1028 The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled. With -schedule-livein-copies: entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1024<def> = MOV32rr %EAX %reg1025<def> = MOV32rr %EDX %reg1026<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0] Much better! llvm-svn: 48307
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-16/+14
| | | | | | failures. llvm-svn: 48223
* When the register allocator runs out of registers, spill a physical register ↵Evan Cheng2008-03-111-6/+5
| | | | | | around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. llvm-svn: 48218
* variadic instructions don't have operand info for variadic arguments.Chris Lattner2008-03-111-1/+2
| | | | llvm-svn: 48208
* If a register operand comes from the variadic part of a node, don'tChris Lattner2008-03-111-4/+6
| | | | | | verify the register constraint matches what the instruction expects. llvm-svn: 48205
* Correctly clone FlaggedNodes.Dan Gohman2008-03-101-2/+1
| | | | llvm-svn: 48196
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-15/+15
| | | | llvm-svn: 48167
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-15/+15
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner2008-03-091-15/+23
| | | | | | | | | | | | an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
* Add ScheduleDAG support for copytoreg where the src/dst register areChris Lattner2008-03-091-16/+19
| | | | | | | | in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) llvm-svn: 48105
* fix 80 col violationChris Lattner2008-03-091-1/+2
| | | | llvm-svn: 48100
* Some improvements related to the computation of heights, depths of SUnits.Roman Levenstein2008-03-041-21/+93
| | | | | | | The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time. llvm-svn: 47884
* Rename isOperand() to isOperandOf() (and other similar methods). It always ↵Evan Cheng2008-03-041-1/+1
| | | | | | confuses me. llvm-svn: 47872
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