summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit message (Collapse)AuthorAgeFilesLines
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-261-3/+3
| | | | | | | | | | | | If we have a binary operation like ISD:ADD, we can set the result type equal to the result type of one of its operands rather than using TargetLowering::getPointerTy(). Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary operation can be replaced with: DAG.getConstant(C, OtherOperand.getValueType()); llvm-svn: 189227
* SelectionDAG: Make sure stores are always added to the LegalizedNodes listTom Stellard2013-08-211-1/+1
| | | | | | | | | | | | | | | | When truncated vector stores were being custom lowered in VectorLegalizer::LegalizeOp(), the old (illegal) and new (legal) node pair was not being added to LegalizedNodes list. Instead of the legalized result being passed to VectorLegalizer::TranslateLegalizeResult(), the result was being passed back into VectorLegalizer::LegalizeOp(), which ended up adding a (new, new) pair to the list instead. This was causing an assertion failure when a custom lowered truncated vector store was the last instruction a basic block and the VectorLegalizer was unable to find it in the LegalizedNodes list when updating the DAG root. llvm-svn: 188953
* Add a llvm.copysign intrinsicHal Finkel2013-08-191-0/+1
| | | | | | | | | | | | | | | | | | | | | This adds a llvm.copysign intrinsic; We already have Libfunc recognition for copysign (which is turned into the FCOPYSIGN SDAG node). In order to autovectorize calls to copysign in the loop vectorizer, we need a corresponding intrinsic as well. In addition to the expected changes to the language reference, the loop vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a few lists in LegalizeVector{Ops,Types} so that vector copysigns can be expanded. In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN be Expand for vector types. This seems correct for all in-tree targets, and I think is the right thing to do because, previously, there was no way to generate vector-values FCOPYSIGN nodes (and most targets don't specify an action for vector-typed FCOPYSIGN). llvm-svn: 188728
* Add ISD::FROUND for libm round()Hal Finkel2013-08-071-0/+1
| | | | | | | | | | | | | | | All libm floating-point rounding functions, except for round(), had their own ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm adding ISD::FROUND so that round() can be custom lowered as well. For the most part, this is straightforward. I've added an intrinsic and a matching ISD node just like those for nearbyint() and friends. The SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed fround). This will be used by the PowerPC backend in a follow-up commit. llvm-svn: 187926
* TargetLowering: Add getVectorIdxTy() function v2Tom Stellard2013-08-051-3/+3
| | | | | | | | | | | | | | | | | | | | | This virtual function can be implemented by targets to specify the type to use for the index operand of INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT, INSERT_SUBVECTOR, EXTRACT_SUBVECTOR. The default implementation returns the result from TargetLowering::getPointerTy() The previous code was using TargetLowering::getPointerTy() for vector indices, because this is guaranteed to be legal on all targets. However, using TargetLowering::getPointerTy() can be a problem for targets with pointer sizes that differ across address spaces. On such targets, when vectors need to be loaded or stored to an address space other than the default 'zero' address space (which is the address space assumed by TargetLowering::getPointerTy()), having an index that is a different size than the pointer can lead to inefficient pointer calculations, (e.g. 64-bit adds for a 32-bit address space). There is no intended functionality change with this patch. llvm-svn: 187748
* Remove trailing whitespace from SelectionDAG/*.cppStephen Lin2013-07-081-1/+1
| | | | llvm-svn: 185780
* Introduce getSelect usage and use more getSelectCCMatt Arsenault2013-06-141-5/+5
| | | | llvm-svn: 184012
* Remove double semicolons.Benjamin Kramer2013-05-281-9/+9
| | | | llvm-svn: 182778
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-10/+10
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-2/+3
| | | | llvm-svn: 182180
* Fix vselect when getSetCCResultType returns a different type from the operandsMatt Arsenault2013-05-071-3/+8
| | | | llvm-svn: 181348
* SelectionDAG compile time improvement.Nadav Rotem2013-02-221-0/+19
| | | | | | | | One of the phases of SelectionDAG is LegalizeVectors. We don't need to sort the DAG and copy nodes around if there are no vector ops. Speeds up the compilation time of SelectionDAG on a big scalar workload by ~8%. llvm-svn: 175929
* Fix PR15267Michael Liao2013-02-201-14/+119
| | | | | | | | | - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
* This patch aims to reduce compile time in LegalizeTypes by using SmallDenseMap,Preston Gurd2013-01-251-1/+1
| | | | | | | | | | | | | with an initial number of elements, instead of DenseMap, which has zero initial elements, in order to avoid the copying of elements when the size changes and to avoid allocating space every time LegalizeTypes is run. This patch will not affect the memory footprint, because DenseMap will increase the element size to 64 when the first element is added. Patch by Wan Xiaofei. llvm-svn: 173448
* When lowering an inreg sext first shift left, then right arithmetically.Benjamin Kramer2013-01-121-3/+3
| | | | | | | Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. llvm-svn: 172322
* PPC: Implement efficient lowering of sign_extend_inreg.Nadav Rotem2013-01-111-1/+25
| | | | llvm-svn: 172269
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-191-2/+2
| | | | | | instead of EVTs. llvm-svn: 170529
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-191-2/+2
| | | | llvm-svn: 170510
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-4/+4
| | | | llvm-svn: 169854
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-111-2/+2
| | | | | | instead of EVTs. llvm-svn: 169844
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-111-2/+2
| | | | llvm-svn: 169841
* Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman2012-11-171-0/+1
| | | | | | Couperus. llvm-svn: 168240
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+1
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* Fix a typo.Nadav Rotem2012-09-021-1/+1
| | | | llvm-svn: 163094
* Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem2012-09-021-4/+3
| | | | | | not sign-extend. llvm-svn: 163086
* Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper2012-09-011-1/+6
| | | | | | | | | zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. llvm-svn: 163075
* Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem2012-08-301-1/+65
| | | | | | | | | | | vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926
* Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper2012-08-301-0/+1
| | | | | | expanded when it isn't legal. llvm-svn: 162894
* 'Promote' vector [su]int_to_fp should widen elements.Jim Grosbach2012-06-281-3/+54
| | | | | | | | | | | Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 llvm-svn: 159378
* When emulating vselect using OR/AND/XOR make sure to bitcast the result back ↵Nadav Rotem2012-04-151-1/+2
| | | | | | to the original type. llvm-svn: 154764
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-1/+1
| | | | llvm-svn: 149816
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Improve code generation for vselect on SSE2:Nadav Rotem2011-10-191-7/+9
| | | | | | | | | When checking the availability of instructions using the TLI, a 'promoted' instruction IS available. It means that the value is bitcasted to another type for which there is an operation. The correct check for the availablity of an instruction is to check if it should be expanded. llvm-svn: 142542
* Fix a bug in the legalization of vector anyext-load and trunc-store. Mem ↵Nadav Rotem2011-10-181-7/+9
| | | | | | Index starts with zero. llvm-svn: 142434
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-181-2/+2
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Removed set, but unused variable.Chad Rosier2011-10-171-1/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142206
* Move the legalization of vector loads and stores into LegalizeVectorOps. In someNadav Rotem2011-10-151-0/+119
| | | | | | cases we need the second type-legalization pass in order to support all cases. llvm-svn: 142060
* white space cleanupsNadav Rotem2011-09-181-5/+4
| | | | llvm-svn: 139994
* Fix the assertion which checks the size of the input operand.Nadav Rotem2011-09-131-1/+1
| | | | llvm-svn: 139633
* Add vselect target support for targets that do not support blend but do supportNadav Rotem2011-09-131-2/+41
| | | | | | xor/and/or (For example SSE2). llvm-svn: 139623
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-2/+2
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* [VECTOR-SELECT]Nadav Rotem2011-07-141-1/+1
| | | | | | | | | | | During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-191-1/+48
| | | | | | | | not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. llvm-svn: 127951
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-2/+2
| | | | llvm-svn: 119990
* Change UpdateNodeOperands' operand and return value from SDValue toDan Gohman2010-06-181-1/+1
| | | | | | SDNode *, since it doesn't care about the ResNo value. llvm-svn: 106282
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-1/+1
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNodeDan Gohman2010-01-091-1/+4
| | | | | | | | | | really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-0/+1
| | | | llvm-svn: 91158
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Added support to allow clients to custom widen. For X86, custom widen ↵Mon P Wang2009-11-301-55/+2
| | | | | | | | | vectors for divide/remainder since these operations can trap by unroll them and adding undefs for the resulting vector. llvm-svn: 90108
OpenPOWER on IntegriCloud