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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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* Remove trailing spaceFangrui Song2018-07-301-9/+9
* Fix corruption of result number in LegalizeVectorOps.cppUlrich Weigand2018-07-251-1/+2
* [Legalize] Elide MERGE_VALUES created by scalarizeVectorLoad.Nirav Dave2018-07-231-3/+8
* [FPEnv] Expand constrained FP POWICameron McInally2018-06-151-4/+18
* [FPEnv] Expand constrained FP operationsCameron McInally2018-06-131-8/+88
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-8/+9
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-16/+16
* DAG: Fix not legalizing vector fcanonicalizesMatt Arsenault2018-04-261-0/+1
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [VectorLegalizer] Fix uint64_t typo in ExpandUINT_TO_FLOAT (PR36391)Simon Pilgrim2018-02-201-1/+1
* [SelectionDAG] Fix codegen of vector stores with non byte-sized elements.Jonas Paulsson2018-01-201-1/+0
* [VectorLegalizer] Remove broken code in ExpandStore.Jonas Paulsson2018-01-111-28/+0
* [SelectionDAG][X86][AArch64] Require targets to specify the promotion type wh...Craig Topper2018-01-011-37/+21
* [SelectionDAG] Add some debug print messages to LegalizeVectorOps.Craig Topper2017-12-281-2/+15
* [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to...Craig Topper2017-11-291-3/+11
* DAG: Add nuw when splitting loads and storesMatt Arsenault2017-11-291-4/+2
* [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of le...Craig Topper2017-11-281-2/+2
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What Yo...Eugene Zelenko2017-09-211-9/+27
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+1
* DAG: Do not scalarize fsub if fneg is legalMatt Arsenault2017-02-151-0/+15
* Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where p...Simon Pilgrim2017-01-301-7/+3
* [SelectionDAG] Add expansion and promotion of [US]MUL_LOHINicolai Haehnle2016-12-081-0/+2
* [VectorLegalizer] Remove EVT::getSizeInBits code duplications. NFCI.Simon Pilgrim2016-11-211-8/+6
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-081-6/+50
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-2/+2
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-141-1/+1
* getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-3/+3
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-1/+1
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore,...Justin Lebar2016-07-151-19/+14
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a poin...Craig Topper2016-07-011-3/+2
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and...Simon Pilgrim2016-05-121-5/+32
* [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED)Simon Pilgrim2016-05-041-2/+2
* Revert r268504Simon Pilgrim2016-05-041-2/+2
* [SelectionDAG] BITREVERSE vector legalization of bit operationsSimon Pilgrim2016-05-041-2/+2
* [SelectionDAG] Teach LegalizeVectorOps to directly Expand CTTZ_ZERO_UNDEF/CTL...Craig Topper2016-04-211-3/+5
* LegalizeDAG: Don't replace vector store with integer if not legalMatt Arsenault2016-03-301-41/+27
* LegalizeDAG: Don't replace vector load with integer unless legalMatt Arsenault2016-03-301-28/+21
* [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_...Simon Pilgrim2016-03-101-1/+1
* [CodeGen] Document and use getConstant's splat-building feature. NFC.Ahmed Bougacha2016-02-151-4/+1
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-2/+1
* [SelectionDAG] Teach LegalizeVectorOps to not unroll CTLZ_ZERO_UNDEF and CTTZ...Craig Topper2015-12-271-0/+14
* AMDGPU: Use generic bitreverse intrinsicMatt Arsenault2015-12-141-1/+24
* Revert r248483, r242546, r242545, and r242409 - absdiff intrinsicsHal Finkel2015-12-111-34/+0
* AVX-512: Fixed masked load / store instruction selection for KNL.Elena Demikhovsky2015-12-071-1/+4
* Fix some places where we were assuming that memory type had been legalizedEric Christopher2015-11-251-1/+1
* Do not use "else" when both branches return (NFC)Mehdi Amini2015-10-271-2/+1
* Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov2015-10-201-0/+1
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