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* [SelectionDAG] Enhance the simplification of `copyto` from `implicit-def`.Michael Liao2019-05-271-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: - The current implementation simplifies the case where the source of `copyto` is `implicit-def`ed. However, it only works when that `implicit-def` is single-used since it detects that from `implicit-def` and cannot determine which destination vreg should be used if there are multiple uses. - This patch changes that detection when `copyto` is being emitted. If that `copyto`'s source is defined from `implicit-def`, it simplifies it. Hence, it works even that `implicit-def` is multi-used. - Except it simplifies the internal IR, it won't improve the quality of code generation. However, it helps to detect 'implicit-def` in a straight-forward manner in some passes, such as `si-i1-copies`. A test case is added. Reviewers: sunfish, nhaehnle Subscribers: jvesely, hiraditya, asbirlea, llvm-commits, yaxunl Tags: #llvm Differential Revision: https://reviews.llvm.org/D62342 llvm-svn: 361777
* [AMDGPU] Divergence driven ISel. Assign register class for cross block ↵Alexander Timofeev2019-05-261-1/+1
| | | | | | | | | | | | | | | | | | values according to the divergence. Details: To make instruction selection really divergence driven it is necessary to assign the correct register classes to the cross block values beforehand. For the divergent targets same value type requires different register classes dependent on the value divergence. Reviewers: rampitec, nhaehnle Differential Revision: https://reviews.llvm.org/D59990 This commit was reverted because of the build failure. The reason was mlformed patch. Build failure fixed. llvm-svn: 361741
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for ↵Peter Collingbourne2019-05-251-1/+1
| | | | | | | | | | cross block values according to the divergence." Broke sanitizer bots: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/21694/steps/bootstrap%20clang/logs/stdio http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/32478/steps/check-llvm%20asan/logs/stdio llvm-svn: 361688
* [AMDGPU] Divergence driven ISel. Assign register class for cross block ↵Alexander Timofeev2019-05-241-1/+1
| | | | | | | | | | | | | | values according to the divergence. Details: To make instruction selection really divergence driven it is necessary to assign the correct register classes to the cross block values beforehand. For the divergent targets same value type requires different register classes dependent on the value divergence. Reviewers: rampitec, nhaehnle Differential Revision: https://reviews.llvm.org/D59990 llvm-svn: 361644
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.Shiva Chen2018-05-091-0/+3
| | | | | | | | | | | | | | | | | | | | | In order to convert LLVM IR to MachineInstr, we need a new TargetOpcode, DBG_LABEL, to ‘lower’ intrinsic llvm.dbg.label. The patch creates this new TargetOpcode and convert intrinsic llvm.dbg.label to MachineInstr through SelectionDAG. In SelectionDAG, debug information is stored in SDDbgInfo. We create a new data member of SDDbgInfo for labels and use the new data member, SDDbgLabel, to create DBG_LABEL MachineInstr. The new DBG_LABEL MachineInstr uses label metadata from LLVM IR as its parameter. So, the backend could get metadata information of labels from DBG_LABEL MachineInstr. Differential Revision: https://reviews.llvm.org/D45341 Patch by Hsiangkai Wang. llvm-svn: 331842
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-2/+2
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Minor code cleanup. NFC.Junmo Park2016-03-261-1/+1
| | | | llvm-svn: 264505
* [SDAG] Give InstrEmitter hidden visibilityBenjamin Kramer2015-07-011-1/+1
| | | | | | NFC. llvm-svn: 241165
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Remove the uses of getSubtargetImpl from InstrEmitter and removeEric Christopher2014-10-091-1/+0
| | | | | | the now unused TargetMachine variable. llvm-svn: 219379
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Revert "Give internal classes hidden visibility."Benjamin Kramer2013-09-111-1/+1
| | | | | | | It works with clang, but GCC has different rules so we can't make all of those hidden. This reverts commit r190534. llvm-svn: 190536
* Give internal classes hidden visibility.Benjamin Kramer2013-09-111-1/+1
| | | | | | Worth 100k on a linux/x86_64 Release+Asserts clang. llvm-svn: 190534
* Add -*- C++ -*- to InstrEmitter.h.Michael Gottesman2013-07-171-1/+1
| | | | llvm-svn: 186527
* Use MachineInstrBuilder in InstrEmitter.Jakob Stoklund Olesen2012-12-201-3/+7
| | | | | | | | | | | | This is supposed to be a mechanical change with no functional effects. InstrEmitter can generate all types of MachineOperands which revealed that MachineInstrBuilder was missing a few methods, added by this patch. Besides providing a context pointer to MI::addOperand(), MachineInstrBuilder seems like a better fit for this code. llvm-svn: 170712
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-131-1/+1
| | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169854
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-111-1/+1
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-2/+2
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen2012-07-041-6/+0
| | | | | | | | | | | | | | | Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. llvm-svn: 159727
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-0/+6
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. llvm-svn: 141207
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-4/+4
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Don't set kill flags for instructions which the scheduler has cloned.Dan Gohman2010-05-141-4/+6
| | | | llvm-svn: 103827
* Teach scheduler about REG_SEQUENCE.Evan Cheng2010-05-041-0/+3
| | | | llvm-svn: 102984
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-5/+3
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* EmitDbgValue doesn't need its EdgeMapping argument.Dan Gohman2010-04-301-2/+1
| | | | llvm-svn: 102742
* - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo ↵Evan Cheng2010-04-261-1/+0
| | | | | | | | and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. llvm-svn: 102323
* reapply 99444/99445, which I speculatively reverted inChris Lattner2010-03-251-1/+13
| | | | | | r99453. llvm-svn: 99482
* Change how dbg_value sdnodes are converted into machine instructions. Their ↵Evan Cheng2010-03-251-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. Here is a theoretical example that illustrates why the placement is important. tmp1 = store tmp1 -> x ... tmp2 = add ... ... call ... store tmp2 -> x Now mem2reg comes along: tmp1 = dbg_value (tmp1 -> x) ... tmp2 = add ... ... call ... dbg_value (tmp2 -> x) When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1. Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers"). This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed. llvm-svn: 99469
* revert 99444/99445. This doesn't cause the failure of Chris Lattner2010-03-241-13/+1
| | | | | | | | 2006-07-19-stwbrx-crash.ll for me, but it's the only likely patch in the blame list of several bots. Lets see if this fixes it. llvm-svn: 99453
* remove dead argument.Chris Lattner2010-03-241-3/+2
| | | | llvm-svn: 99445
* split EmitNode in half to reduce indentation.Chris Lattner2010-03-241-1/+14
| | | | llvm-svn: 99444
* Progress towards shepherding debug info through SelectionDAG.Dale Johannesen2010-03-101-1/+2
| | | | | | | No functional effect yet. This is still evolving and should not be viewed as final. llvm-svn: 98195
* Add some new bits of debug info handling. NoDale Johannesen2010-03-061-0/+11
| | | | | | functional change yet. llvm-svn: 97855
* Fix a typo in a comment.Dan Gohman2009-11-161-1/+1
| | | | llvm-svn: 88953
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-0/+119
into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
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