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path: root/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-1/+1
| | | | | | No functional change. llvm-svn: 132455
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-4/+4
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Optimize:Evan Cheng2011-01-051-23/+39
| | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 llvm-svn: 122925
* flags -> glue for selectiondagChris Lattner2010-12-231-10/+10
| | | | llvm-svn: 122509
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-6/+6
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-9/+9
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-3/+1
| | | | | | Radar 8776599 llvm-svn: 122018
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121293
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-161-13/+0
| | | | | | | easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. llvm-svn: 119382
* Revert r112461. It was failing on PPC...Bill Wendling2010-08-301-4/+2
| | | | llvm-svn: 112463
* When adding a register, we should mark it as "def" if it can optionally defineBill Wendling2010-08-301-2/+4
| | | | | | said (physical) register. llvm-svn: 112461
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-101-34/+9
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. llvm-svn: 108050
* Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman2010-07-101-1/+1
| | | | | | at the end of the block. llvm-svn: 108045
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+7
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-2/+7
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-7/+9
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-5/+2
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Not all custom inserters create new basic blocks. If the inserterDan Gohman2010-07-071-2/+5
| | | | | | didn't create a new block, don't reset the insert position. llvm-svn: 107813
* Update comment.Devang Patel2010-07-071-3/+4
| | | | llvm-svn: 107796
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-2/+5
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-021-0/+6
| | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. llvm-svn: 107506
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-4/+4
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-181-0/+27
| | | | | | on calls and similar instructions. llvm-svn: 106353
* Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen2010-06-091-2/+6
| | | | | | | This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. llvm-svn: 105749
* Add argument name comments.Jakob Stoklund Olesen2010-06-091-2/+6
| | | | llvm-svn: 105665
* Continuously refine the register class of REG_SEQUENCE def with all the ↵Evan Cheng2010-05-181-2/+3
| | | | | | source registers and sub-register indices. llvm-svn: 104051
* Fix PR7162: Use source register classes and sub-indices to determine the ↵Evan Cheng2010-05-181-4/+6
| | | | | | correct register class of the definitions of REG_SEQUENCE. llvm-svn: 104050
* Don't set kill flags for instructions which the scheduler has cloned.Dan Gohman2010-05-141-16/+28
| | | | llvm-svn: 103827
* Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn'tDan Gohman2010-05-111-9/+16
| | | | | | | create separate virtual registers for CopyFromReg values, so uses of them don't necessarily kill the value. llvm-svn: 103519
* Indentation.Evan Cheng2010-05-101-4/+4
| | | | llvm-svn: 103441
* SDDbgValues are apparently not being legalized. Fix a symptom of the problem,Dan Gohman2010-05-071-1/+7
| | | | | | | and not the real problem itself, by dropping debug info for i128 values. rdar://7958162. llvm-svn: 103310
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Teach scheduler about REG_SEQUENCE.Evan Cheng2010-05-041-2/+41
| | | | llvm-svn: 102984
* Re-enable isel kill flags, now that the local allocator is ignoring them.Dan Gohman2010-05-041-4/+0
| | | | llvm-svn: 102981
* Re-disable kill flags, as there is more trouble.Dan Gohman2010-05-011-0/+4
| | | | llvm-svn: 102826
* Re-enable kill flags from SelectionDAGISel, with a fix: don'tDan Gohman2010-05-011-5/+1
| | | | | | try to put a kill flag on a DBG_INFO instruction. llvm-svn: 102820
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-3/+2
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* EmitDbgValue doesn't need its EdgeMapping argument.Dan Gohman2010-04-301-3/+3
| | | | llvm-svn: 102742
* Temporarily disable SelectionDAG kill flags, which are causing trouble.Dan Gohman2010-04-301-0/+4
| | | | llvm-svn: 102680
* Set register kill flags on the SelectionDAG path, at least in theDan Gohman2010-04-301-1/+12
| | | | | | easy cases. llvm-svn: 102678
* Avoid adding a null MD node operand, which crashes with "-debug" when tryingBob Wilson2010-04-261-1/+2
| | | | | | to print the operand. llvm-svn: 102395
* - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo ↵Evan Cheng2010-04-261-3/+1
| | | | | | | | and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. llvm-svn: 102323
* Stop abusing EmitInstrWithCustomInserter for target-dependentDale Johannesen2010-04-251-9/+8
| | | | | | | | form of DEBUG_VALUE, as it doesn't have reasonable default behavior for unsupported targets. Add a new hook instead. No functional change. llvm-svn: 102320
* Delete a redundant return statement.Dan Gohman2010-04-201-1/+0
| | | | llvm-svn: 101860
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-3/+3
| | | | llvm-svn: 101334
* Have the inst emitter add the !srcloc mdnode to the machine instr.Chris Lattner2010-04-071-0/+6
| | | | | | | Have the asmprinter use the mdnode to scavenge a source location if present. Document this nonsense in langref. llvm-svn: 100607
* Three changes:Chris Lattner2010-04-071-9/+9
| | | | | | | | | | | | | | | 1. Introduce some enums and accessors in the InlineAsm class that eliminate a ton of magic numbers when handling inline asm SDNode. 2. Add a new MDNodeSDNode selection dag node type that holds a MDNode (shocking!) 3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc metadata, propagating it to the instruction emitter, which drops it. No functionality change. llvm-svn: 100605
* Allow for the possibility that a debug-value pointsDale Johannesen2010-04-061-2/+13
| | | | | | to a SDNode that didn't have code generated for it. llvm-svn: 100566
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