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authorEvan Cheng <evan.cheng@apple.com>2010-05-18 20:07:47 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-18 20:07:47 +0000
commit45b3f702abf11617e6cd5f2a33a84966c26015c0 (patch)
treeaf83704b0bde6a435ffb091bf623326d3055b292 /llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
parente7fc64a5c96f53ac0e028ca46930116823d5048a (diff)
downloadbcm5719-llvm-45b3f702abf11617e6cd5f2a33a84966c26015c0.tar.gz
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Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
llvm-svn: 104051
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 2f8f255b5b5..16eb8a72adc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -551,11 +551,12 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
const TargetRegisterClass *SRC =
TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
- //getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
if (!SRC)
llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
- if (SRC != RC)
+ if (SRC != RC) {
MRI->setRegClass(NewVReg, SRC);
+ RC = SRC;
+ }
}
AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned);
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