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path: root/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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* [inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier2012-10-301-8/+2
* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-301-0/+7
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
* Fix PR11985Michael Liao2012-09-121-0/+1
* Remove an overly-aggressive assertion. The code following this assertion alr...Owen Anderson2012-09-121-2/+0
* Add a new optimization pass: Stack Coloring, that merges disjoint static allo...Nadav Rotem2012-09-061-0/+11
* Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen2012-08-311-6/+2
* Don't enforce ordered inline asm operands.Jakob Stoklund Olesen2012-08-311-10/+0
* Verify the order of tied operands in inline asm.Jakob Stoklund Olesen2012-08-291-0/+12
* Set the isTied flags when building INLINEASM MachineInstrs.Jakob Stoklund Olesen2012-08-291-4/+21
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-071-0/+4
* InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng2012-07-111-1/+2
* Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen2012-07-041-7/+27
* Clear kill flags in InstrEmitter::EmitSubregNode().Jakob Stoklund Olesen2012-06-291-0/+1
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-3/+3
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-6/+10
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-031-43/+46
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+2
* Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstr...Pete Cooper2012-01-181-7/+12
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+46
* Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+19
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-1/+2
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-221-3/+5
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-0/+2
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+2
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-2/+1
* whitespaceAndrew Trick2011-09-201-26/+26
* Follow up to r138791.Evan Cheng2011-08-301-0/+4
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-1/+1
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-16/+16
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-3/+3
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-0/+1
* Handle debug info for i128 constants.Devang Patel2011-06-241-6/+2
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi...Owen Anderson2011-06-161-5/+6
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-1/+1
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-4/+4
* Optimize:Evan Cheng2011-01-051-23/+39
* flags -> glue for selectiondagChris Lattner2010-12-231-10/+10
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-6/+6
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-9/+9
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-3/+1
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-161-13/+0
* Revert r112461. It was failing on PPC...Bill Wendling2010-08-301-4/+2
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