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path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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* A select between a constant and zero, when fed by a bit test, can be efficientlyOwen Anderson2010-09-221-0/+29
| | | | | | | lowered using a series of shifts. Fixes <rdar://problem/8285015>. llvm-svn: 114599
* Reimplement r114460 in target-independent DAGCombine rather than ↵Owen Anderson2010-09-211-0/+14
| | | | | | | | | target-dependent, by using the predicate to discover the number of sign bits. Enhance X86's target lowering to provide a useful response to this query. llvm-svn: 114473
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-14/+8
| | | | llvm-svn: 114461
* eliminate an old SelectionDAG::getTruncStore method, propagatingChris Lattner2010-09-211-7/+4
| | | | | | MachinePointerInfo around more. llvm-svn: 114452
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-211-28/+22
| | | | | | SelectionDAG::getExtLoad overload, and eliminate it. llvm-svn: 114446
* convert dagcombine off the old form of getLoad. This fixes several bugs Chris Lattner2010-09-211-16/+18
| | | | | | with SVOffset computation. llvm-svn: 114442
* simplify DAGCombiner::SimplifySelectOps step #2/2.Chris Lattner2010-09-211-55/+53
| | | | llvm-svn: 114437
* substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.Chris Lattner2010-09-211-85/+76
| | | | | | no functionality change (step #1) llvm-svn: 114436
* a few more trivial updates. This fixes PerformInsertVectorEltInMemory to notChris Lattner2010-09-211-1/+1
| | | | | | | pass a completely incorrect SrcValue, which would result in a miscompile with combiner-aa. llvm-svn: 114411
* When TCO is turned on, it is possible to end up with aliasing FrameIndex's. ↵Owen Anderson2010-09-201-2/+13
| | | | | | | | | | | | Therefore, CombinerAA cannot assume that different FrameIndex's never alias, but can instead use MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing. This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll when CombinerAA is enabled, modulo a different register allocation sequence. llvm-svn: 114348
* Revert r114312 while I sort out some issues.Owen Anderson2010-09-191-1/+1
| | | | llvm-svn: 114313
* Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,Owen Anderson2010-09-191-1/+1
| | | | | | | r114268 fixed the last of the blockers to enabling it. I will be monitoring for failures. llvm-svn: 114312
* Don't narrow the load and store in a load+twiddle+store sequence unlessDan Gohman2010-09-021-1/+2
| | | | | | | | | | there are clearly no stores between the load and the store. This fixes this miscompile reported as PR7833. This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is safe, but awkward to prove safe. Move it to X86's README.txt. llvm-svn: 112861
* Fix a crash in the dag combiner caused by ↵Nate Begeman2010-07-271-2/+10
| | | | | | | | ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. llvm-svn: 109519
* Remove r108639 now that it is handled by InstCombine instead.Owen Anderson2010-07-191-13/+0
| | | | llvm-svn: 108688
* Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson2010-07-181-0/+13
| | | | | | | | | | conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. llvm-svn: 108639
* Convert some tab stops into spaces.Duncan Sands2010-07-121-28/+28
| | | | llvm-svn: 108130
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-2/+0
| | | | | | | | disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. llvm-svn: 107941
* Merge the duplicated iabs optimization in DAGCombiner and let it detected a ↵Benjamin Kramer2010-07-081-30/+26
| | | | | | few more idioms. llvm-svn: 107868
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-071-22/+23
| | | | | | for consistency sake. llvm-svn: 107820
* Propagate debug loc.Devang Patel2010-07-061-2/+2
| | | | llvm-svn: 107710
* Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson2010-06-281-1/+2
| | | | | | | can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. llvm-svn: 107097
* Remove variables which are assigned to but for which the valueDuncan Sands2010-06-251-1/+0
| | | | | | is not used. Spotted by gcc-4.6. llvm-svn: 106854
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-241-8/+37
| | | | llvm-svn: 106746
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar2010-06-231-37/+8
| | | | | | DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. llvm-svn: 106634
* Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach2010-06-231-0/+55
| | | | | | | | atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. llvm-svn: 106630
* Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,Dan Gohman2010-06-181-8/+37
| | | | | | which is faster, simpler, and less surprising. llvm-svn: 106263
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-251-1/+5
| | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. llvm-svn: 104624
* Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen2010-05-251-2/+10
| | | | | | | (oye, a word which should be better known to people writing tree traversals, means grandchild.) llvm-svn: 104619
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
| | | | llvm-svn: 104410
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-211-0/+7
| | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. llvm-svn: 104380
* Optimize away insertelement of an undef value. This shows up inBob Wilson2010-05-191-0/+4
| | | | | | | test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. llvm-svn: 104185
* Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng2010-05-191-6/+75
| | | | | | | | | | modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. llvm-svn: 104094
* Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng2010-05-181-4/+0
| | | | | | into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
* FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op ↵Evan Cheng2010-05-181-7/+8
| | | | | | (build_vector), (build_vector)). llvm-svn: 104004
* Be careful with operand promotion. For a binary operation, the source ↵Evan Cheng2010-05-101-4/+10
| | | | | | operands may be the same. PR7018. rdar://7939869. llvm-svn: 103419
* Apply a patch from Jan Sjodin to fix a compiler abort on vectorDan Gohman2010-04-301-9/+24
| | | | | | | comparisons sign-extended to a different bitwidth than the comparison operands. llvm-svn: 102721
* Try operation promotion only if regular dag combine and target-specific ones ↵Evan Cheng2010-04-281-15/+42
| | | | | | failed to do anything. llvm-svn: 102492
* - When legal, promote a load to zextload rather than ext load.Evan Cheng2010-04-271-6/+20
| | | | | | - Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x) llvm-svn: 102455
* When a load operand is promoted to an extload, replace other uses with uses ↵Evan Cheng2010-04-241-30/+67
| | | | | | of extload result truncated. llvm-svn: 102236
* Apply a fix for a vector setcc dagcombine from Jan Sjodin. NoDan Gohman2010-04-241-1/+2
| | | | | | testcase yet, as the testcase now fails downstream. llvm-svn: 102228
* Code refactoring.Evan Cheng2010-04-231-11/+12
| | | | llvm-svn: 102202
* - It's not safe to promote rotates (at least not trivially).Evan Cheng2010-04-221-25/+46
| | | | | | - Some code refactoring. llvm-svn: 102111
* The visitXOR method can return the same SDNode. If so, we don't want to deleteBill Wendling2010-04-201-1/+1
| | | | | | it as it's not dead. llvm-svn: 101855
* More progress on promoting i16 operations to i32 for x86. Work in progress.Evan Cheng2010-04-191-9/+118
| | | | llvm-svn: 101808
* More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng2010-04-171-24/+96
| | | | llvm-svn: 101621
* (i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test ↵Evan Cheng2010-04-161-1/+2
| | | | | | case until -promote-16bit is enabled. llvm-svn: 101551
* Adding support for dag combiner to promote operations for profit. This ↵Evan Cheng2010-04-161-6/+47
| | | | | | | | | | requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. x86 support is off by default. It can be enabled with -promote-16bit. Work in progress. llvm-svn: 101448
* enhance the load/store narrowing optimization to handle aChris Lattner2010-04-151-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | tokenfactor in between the load/store. This allows us to optimize test7 into: _test7: ## @test7 ## BB#0: ## %entry movl (%rdx), %eax ## kill: SIL<def> ESI<kill> movb %sil, 5(%rdi) ret instead of: _test7: ## @test7 ## BB#0: ## %entry movl 4(%esp), %ecx movl $-65281, %eax ## imm = 0xFFFFFFFFFFFF00FF andl 4(%ecx), %eax movzbl 8(%esp), %edx shll $8, %edx addl %eax, %edx movl 12(%esp), %eax movl (%eax), %eax movl %edx, 4(%ecx) ret llvm-svn: 101355
* teach codegen to turn trunc(zextload) into load when possible.Chris Lattner2010-04-151-1/+1
| | | | | | | | This doesn't occur much at all, it only seems to formed in the case when the trunc optimization kicks in due to phase ordering. In that case it is saves a few bytes on x86-32. llvm-svn: 101350
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