| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [DAGCombine] Move AND nodes to multiple load leaves | Sam Parker | 2017-12-14 | 1 | -0/+124 |
| * | [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579) | Sanjay Patel | 2017-12-11 | 1 | -1/+2 |
| * | [DAGCombiner] Add combined indexed load to the work list | Nemanja Ivanovic | 2017-12-11 | 1 | -0/+1 |
| * | [ARM] Use ADDCARRY / SUBCARRY | Roger Ferrer Ibanez | 2017-12-11 | 1 | -1/+2 |
| * | [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors. | Craig Topper | 2017-12-11 | 1 | -0/+16 |
| * | [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC | Craig Topper | 2017-12-11 | 1 | -4/+3 |
| * | [DAGCombiner] eliminate shuffle of insert element | Sanjay Patel | 2017-12-07 | 1 | -0/+81 |
| * | [ARM][AArch64][DAG] Reenable post-legalize store merge | Nirav Dave | 2017-12-06 | 1 | -12/+19 |
| * | Revert "[DAGCombine] Move AND nodes to multiple load leaves" | Vlad Tsyrklevich | 2017-12-06 | 1 | -123/+0 |
| * | [DAGCombine] Move AND nodes to multiple load leaves | Sam Parker | 2017-12-05 | 1 | -0/+123 |
| * | [DAGCombine] Handle big endian correctly in CombineConsecutiveLoads | Bjorn Pettersson | 2017-12-05 | 1 | -0/+7 |
| * | [DAGCombine] isLegalNarrowLoad function (NFC) | Sam Parker | 2017-12-05 | 1 | -42/+60 |
| * | DAG: Follow-up to r319692 check the truncates inputs have the same type | Hans Wennborg | 2017-12-04 | 1 | -1/+2 |
| * | DAG: Match truncated rotation (PR35487) | Hans Wennborg | 2017-12-04 | 1 | -0/+9 |
| * | [DAGCombine] Remove isAndLoadExtLoad arguments | Sam Parker | 2017-12-04 | 1 | -14/+6 |
| * | [DAG][ARM] Revert "Reenable post-legalize store merge" | Nirav Dave | 2017-12-01 | 1 | -11/+5 |
| * | [DAGCombine] Simplify ISD::AND handling in ReduceLoadWidth | Eli Friedman | 2017-12-01 | 1 | -20/+5 |
| * | [ARM][DAG] Reenable post-legalize store merge | Nirav Dave | 2017-12-01 | 1 | -5/+11 |
| * | [DAGCombine] Refactor ReduceLoadWidth | Sam Parker | 2017-11-30 | 1 | -50/+33 |
| * | Use getStoreSize() in various places instead of 'BitSize >> 3'. | Jonas Paulsson | 2017-11-28 | 1 | -8/+8 |
| * | [DAGCombine] Disable finding better chains for stores at O0 | Simon Dardis | 2017-11-28 | 1 | -1/+8 |
| * | [DAGCombiner] Don't combine aext(setcc) if the setcc is already using the tar... | Craig Topper | 2017-11-27 | 1 | -8/+11 |
| * | [DAGCombiner] Use EVT::changeVectorElementTypeToInteger() instead of implemen... | Craig Topper | 2017-11-27 | 1 | -4/+1 |
| * | [DAGCombiner] Bugfix in isAlias(). | Jonas Paulsson | 2017-11-22 | 1 | -2/+2 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -3/+3 |
| * | [DAGCombiner] Use cast instead of an unchecked dyn_cast. | Craig Topper | 2017-11-16 | 1 | -1/+1 |
| * | [DAGCombine] Enable more srl -> load combines | Sam Parker | 2017-11-16 | 1 | -5/+16 |
| * | [DAGcombine] Do not replace truncate node by itself when doing constant foldi... | Amaury Sechet | 2017-11-10 | 1 | -3/+9 |
| * | Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask). | Adrian Prantl | 2017-11-09 | 1 | -1/+5 |
| * | [DAGCombiner] Fix typos in comments. NFC | Craig Topper | 2017-11-01 | 1 | -2/+2 |
| * | [DAGCombine] Don't combine sext with extload if sextload is not supported and... | Guozhi Wei | 2017-10-27 | 1 | -1/+5 |
| * | DAG: Fold fma (fneg x), K, y -> fma x, -K, y | Matt Arsenault | 2017-10-27 | 1 | -0/+8 |
| * | [DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORs | Simon Pilgrim | 2017-10-23 | 1 | -5/+15 |
| * | [DAGCombine] Add SCALAR_TO_VECTOR undef handling to simplifyShuffleMask. | Simon Pilgrim | 2017-10-17 | 1 | -2/+6 |
| * | DAG: Add opcode and source type to isFPExtFree | Matt Arsenault | 2017-10-13 | 1 | -235/+253 |
| * | Revert r307036 because of PR34919. | Wei Mi | 2017-10-12 | 1 | -92/+0 |
| * | [DAGCombiner] convert insertelement of bitcasted vector into shuffle | Sanjay Patel | 2017-10-11 | 1 | -3/+62 |
| * | [DAGCombine] Fix for shuffle to vector extend for non power 2 vectors | David Stuttard | 2017-10-10 | 1 | -0/+3 |
| * | [DAG] combine assertsexts around a trunc | Sanjay Patel | 2017-10-09 | 1 | -10/+10 |
| * | Eliminate ftrunc if source is know to be rounded | Stanislav Mekhanoshin | 2017-10-02 | 1 | -0/+13 |
| * | [DAGCombiner] Fix an off-by-one error in vector logic | George Burgess IV | 2017-09-28 | 1 | -2/+2 |
| * | [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What Yo... | Eugene Zelenko | 2017-09-21 | 1 | -99/+114 |
| * | [DAGCombiner] Slightly simplify some code by using APInt::isMask() and countT... | Craig Topper | 2017-09-21 | 1 | -3/+3 |
| * | [DAGCombiner] Remove duplicate code from visitZERO_EXTEND | Craig Topper | 2017-09-21 | 1 | -14/+0 |
| * | [DAGCombiner] fold assertzexts separated by trunc | Sanjay Patel | 2017-09-18 | 1 | -2/+25 |
| * | [DAG, x86] allow store merging before and after legalization (PR34217) | Sanjay Patel | 2017-09-18 | 1 | -4/+4 |
| * | [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) | Simon Pilgrim | 2017-09-14 | 1 | -2/+4 |
| * | DAG: Allow creating extract_vector_elt post-legalize | Matt Arsenault | 2017-09-07 | 1 | -1/+4 |
| * | [DAGCombiner] When combining EXTRACT_SUBVECTOR of a BUILD_VECTOR, make sure w... | Craig Topper | 2017-09-06 | 1 | -2/+3 |
| * | [X86] Fix crash on assert of non-simple type after type-legalization | Ayman Musa | 2017-09-03 | 1 | -5/+7 |
