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path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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* Make DAGCombiner's global alias analysis query more precise in the caseDan Gohman2007-08-271-2/+3
| | | | | | where both pointers have non-zero offsets. llvm-svn: 41491
* Revise per review comments.Dale Johannesen2007-08-261-1/+1
| | | | llvm-svn: 41409
* Add APFloat interface to ConstantFPSDNode. ChangeDale Johannesen2007-08-251-10/+6
| | | | | | | over uses in DAGCombiner. Fix interfaces to work with APFloats. llvm-svn: 41407
* Fold C ? 0 : 1 to ~C or zext(~C) or trunc(~C) depending the types.Evan Cheng2007-08-181-3/+14
| | | | llvm-svn: 41163
* Fix the alias analysis query in DAGCombiner to not add in twoDan Gohman2007-07-261-2/+2
| | | | | | | offsets. The SrcValueOffset values are the real offsets from the SrcValue base pointers. llvm-svn: 40534
* Don't call SimplifyVBinOp for non-vector operations, following earlier reviewDan Gohman2007-07-131-25/+49
| | | | | | feedback. This theoretically makes the common (scalar) case more efficient. llvm-svn: 39823
* Fix a bug in the folding of binary operators to undef.Dan Gohman2007-07-101-4/+10
| | | | | | Thanks to Lauro for spotting this! llvm-svn: 38491
* Fix the folding of undef in several binary operators to recognizeDan Gohman2007-07-101-7/+7
| | | | | | undef in either the left or right operand. llvm-svn: 38489
* Preserve volatililty and alignment information when lowering orDan Gohman2007-07-091-9/+22
| | | | | | simplifying loads and stores. llvm-svn: 38473
* Fix this warning:Chris Lattner2007-07-091-1/+1
| | | | | | | | | DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)': DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)' oiy. llvm-svn: 38458
* Fix several over-aggressive folds for undef nodes in dagcombine, toDan Gohman2007-07-031-51/+46
| | | | | | follow the rules for undef used in instcombine. llvm-svn: 37851
* Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, andDan Gohman2007-07-021-11/+14
| | | | | | | | | | visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG to use isNegatibleForFree/GetNegatedExpression instead of doing a subset of the same thing manually. This fixes test/CodeGen/X86/negative-sin.ll. llvm-svn: 37842
* Generalize MVT::ValueType and associated functions to be able to representDan Gohman2007-06-251-292/+240
| | | | | | | | | | | | | | | extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
* Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits fromDan Gohman2007-06-221-23/+23
| | | | | | | | | TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. llvm-svn: 37704
* Xforms:Evan Cheng2007-06-211-0/+64
| | | | | | | (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) llvm-svn: 37685
* Pass a SelectionDAG into SDNode::dump everywhere it's used, in preprationDan Gohman2007-06-191-5/+5
| | | | | | | for needing the DAG node to print pre-legalize extended value types, and to get better debug messages with target-specific nodes. llvm-svn: 37656
* Rename MVT::getVectorBaseType to MVT::getVectorElementType.Dan Gohman2007-06-141-1/+1
| | | | llvm-svn: 37579
* tighten up recursion depth againChris Lattner2007-05-251-11/+13
| | | | llvm-svn: 37330
* Fix a typo that caused combiner to create mal-formed pre-indexed store where ↵Evan Cheng2007-05-241-6/+6
| | | | | | value store is the same as the base pointer. llvm-svn: 37318
* prevent exponential recursion in isNegatibleForFreeChris Lattner2007-05-231-6/+9
| | | | llvm-svn: 37310
* Qualify calls to getTypeForValueType with MVT:: too.Dan Gohman2007-05-181-3/+3
| | | | llvm-svn: 37233
* Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.Dale Johannesen2007-05-161-1/+3
| | | | llvm-svn: 37130
* Use a ptr set instead of a linear search to unique TokenFactor operands.Chris Lattner2007-05-161-10/+13
| | | | | | This fixes PR1423 llvm-svn: 37102
* Bug fix: should check ABI alignment, not pref. alignment.Evan Cheng2007-05-161-2/+2
| | | | llvm-svn: 37094
* Fix an infinite recursion in GetNegatedExpression.Lauro Ramos Venancio2007-05-151-1/+1
| | | | llvm-svn: 37086
* implement a simple fneg optimization/propagation thing. This compiles:Chris Lattner2007-05-141-7/+144
| | | | | | | | | | | | | | | | | | | CodeGen/PowerPC/fneg.ll into: _t4: fmul f0, f3, f4 fmadd f1, f1, f2, f0 blr instead of: _t4: fneg f0, f3 fmul f0, f0, f4 fmsub f1, f1, f2, f0 blr llvm-svn: 37054
* Can't fold the bit_convert is the store is a truncating store.Evan Cheng2007-05-091-2/+2
| | | | llvm-svn: 36962
* Forgot a check.Evan Cheng2007-05-071-1/+1
| | | | llvm-svn: 36910
* Enable a couple of xforms:Evan Cheng2007-05-071-16/+27
| | | | | | | | | - (store (bitconvert v)) -> (store v) if resultant store does not require higher alignment - (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not require higher alignment llvm-svn: 36908
* Don't create indexed load / store with zero offset!Evan Cheng2007-05-031-0/+8
| | | | llvm-svn: 36716
* Forgot about chain result; also UNDEF cannot have multiple values.Evan Cheng2007-05-011-12/+12
| | | | llvm-svn: 36622
* * Only turn a load to UNDEF if all of its outputs have no uses (indexed loadsEvan Cheng2007-05-011-5/+20
| | | | | | | produce two results.) * Do not touch volatile loads. llvm-svn: 36604
* PR400 phase 2. Propagate attributed load/store information through DAGs.Christopher Lamb2007-04-221-19/+51
| | | | llvm-svn: 36356
* Revert Christopher Lamb's load/store alignment changes.Reid Spencer2007-04-211-51/+19
| | | | llvm-svn: 36309
* add support for alignment attributes on load/store instructionsChristopher Lamb2007-04-211-19/+51
| | | | llvm-svn: 36301
* allow SRL to simplify its operands, as it doesn't demand all bits as input.Chris Lattner2007-04-181-1/+7
| | | | llvm-svn: 36245
* When replacing a node in SimplifyDemandedBits, if the old node used anyChris Lattner2007-04-181-1/+8
| | | | | | | single-use nodes, they will be dead soon. Make sure to remove them before processing other nodes. This implements CodeGen/X86/shl_elim.ll llvm-svn: 36244
* SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBitsChris Lattner2007-04-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | a chance to hack on it. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr instead of: _baz: srwi r2, r4, 24 rlwimi r2, r3, 8, 0, 23 srwi r2, r2, 9 extsh r3, r2 blr This implements CodeGen/PowerPC/sign_ext_inreg1.ll llvm-svn: 36212
* fix an infinite loop compiling ldecod, notice by JeffC.Chris Lattner2007-04-111-1/+1
| | | | llvm-svn: 35910
* Fix this harder.Chris Lattner2007-04-111-12/+19
| | | | llvm-svn: 35888
* don't create shifts by zero, fix some problems with my previous patchChris Lattner2007-04-111-3/+7
| | | | llvm-svn: 35887
* Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner2007-04-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll llvm-svn: 35883
* Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner2007-04-111-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) llvm-svn: 35881
* 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel2007-04-021-22/+59
| | | | | | | | | 2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. llvm-svn: 35605
* Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen2007-03-301-3/+1
| | | | | | combination. llvm-svn: 35517
* Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng2007-03-291-1/+3
| | | | | | big endian targets until llvm-gcc build issue has been resolved. llvm-svn: 35449
* SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng2007-03-261-2/+6
| | | | llvm-svn: 35350
* Adjust offset to compensate for big endian machines.Evan Cheng2007-03-241-7/+5
| | | | llvm-svn: 35293
* Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng2007-03-231-0/+4
| | | | llvm-svn: 35289
* Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng2007-03-231-1/+8
| | | | llvm-svn: 35286
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