| Commit message (Collapse) | Author | Age | Files | Lines |
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encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
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llvm-svn: 117720
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Also do some minor refactoring to reduce indentation.
llvm-svn: 117558
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llvm-svn: 116890
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// %a = ...
// %b = and i32 %a, 2
// %c = srl i32 %b, 1
// brcond i32 %c ...
//
// into
//
// %a = ...
// %b = and i32 %a, 2
// %c = setcc eq %b, 0
// brcond %c ...
Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.
This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.
llvm-svn: 115571
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llvm-svn: 115294
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lowered using a series of shifts.
Fixes <rdar://problem/8285015>.
llvm-svn: 114599
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target-dependent, by using
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
llvm-svn: 114473
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llvm-svn: 114461
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MachinePointerInfo around more.
llvm-svn: 114452
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SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
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with SVOffset computation.
llvm-svn: 114442
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llvm-svn: 114437
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no functionality change (step #1)
llvm-svn: 114436
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pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.
llvm-svn: 114411
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Therefore,
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.
This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.
llvm-svn: 114348
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llvm-svn: 114313
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r114268 fixed the last of the blockers to enabling it. I will be monitoring
for failures.
llvm-svn: 114312
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there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
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ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.
llvm-svn: 109519
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llvm-svn: 108688
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conversions around sqrt instructions.
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.
This fixed <rdar://problem/8197504>.
llvm-svn: 108639
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llvm-svn: 108130
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disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
llvm-svn: 107941
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few more idioms.
llvm-svn: 107868
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for consistency sake.
llvm-svn: 107820
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llvm-svn: 107710
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can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
llvm-svn: 107097
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is not used. Spotted by gcc-4.6.
llvm-svn: 106854
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llvm-svn: 106746
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DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
llvm-svn: 106634
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atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
llvm-svn: 106630
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which is faster, simpler, and less surprising.
llvm-svn: 106263
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Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
llvm-svn: 104624
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(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
llvm-svn: 104619
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llvm-svn: 104410
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
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modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
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into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
llvm-svn: 104060
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(build_vector), (build_vector)).
llvm-svn: 104004
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operands may be the same. PR7018. rdar://7939869.
llvm-svn: 103419
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comparisons sign-extended to a different bitwidth than the
comparison operands.
llvm-svn: 102721
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failed to do anything.
llvm-svn: 102492
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- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)
llvm-svn: 102455
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of extload result truncated.
llvm-svn: 102236
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testcase yet, as the testcase now fails downstream.
llvm-svn: 102228
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llvm-svn: 102202
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- Some code refactoring.
llvm-svn: 102111
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it as it's not dead.
llvm-svn: 101855
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