| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 42824
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Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.
llvm-svn: 42759
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llvm-svn: 42692
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llvm-svn: 42686
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(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.
llvm-svn: 42677
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shuffle <undef, undef, x, undef>, <undef, undef, undef, undef>, <2, 2, 2, 2>
!=
<undef, undef, x, undef>
llvm-svn: 42111
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llvm-svn: 42103
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Next round of x87 long double stuff.
Getting close now, basically works.
llvm-svn: 41875
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access to bits). Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling
(untested, probably does not work).
llvm-svn: 41858
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cmpl %eax, %ecx
setae %al
movzbl %al, %eax
instead of:
cmpl %eax, %ecx
setb %al
xorb $1, %al
movzbl %al, %eax
when using logical not of a C comparison.
llvm-svn: 41807
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Implement some constant folding in SelectionDAG and
DAGCombiner using APFloat. Remove double versions
of constructor and getValue from ConstantFPSDNode.
llvm-svn: 41664
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where both pointers have non-zero offsets.
llvm-svn: 41491
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llvm-svn: 41409
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over uses in DAGCombiner. Fix interfaces to work
with APFloats.
llvm-svn: 41407
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llvm-svn: 41163
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offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
llvm-svn: 40534
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feedback. This theoretically makes the common (scalar) case more efficient.
llvm-svn: 39823
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Thanks to Lauro for spotting this!
llvm-svn: 38491
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undef in either the left or right operand.
llvm-svn: 38489
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simplifying loads and stores.
llvm-svn: 38473
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DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'
oiy.
llvm-svn: 38458
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follow the rules for undef used in instcombine.
llvm-svn: 37851
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visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.
This fixes test/CodeGen/X86/negative-sin.ll.
llvm-svn: 37842
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
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(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
llvm-svn: 37685
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
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llvm-svn: 37579
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llvm-svn: 37330
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value store is the same as the base pointer.
llvm-svn: 37318
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llvm-svn: 37310
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llvm-svn: 37233
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llvm-svn: 37130
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This fixes PR1423
llvm-svn: 37102
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llvm-svn: 37094
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llvm-svn: 37086
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CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
llvm-svn: 37054
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llvm-svn: 36962
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llvm-svn: 36910
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- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
llvm-svn: 36908
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llvm-svn: 36716
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llvm-svn: 36622
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produce two results.)
* Do not touch volatile loads.
llvm-svn: 36604
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llvm-svn: 36356
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llvm-svn: 36309
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llvm-svn: 36301
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llvm-svn: 36245
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single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
llvm-svn: 36244
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a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
llvm-svn: 36212
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llvm-svn: 35910
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