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path: root/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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* misched: Compress pairs returned by getUnderlyingObjectsForInstr.Benjamin Kramer2013-06-291-12/+15
| | | | llvm-svn: 185266
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-17/+7
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-131-0/+4
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* Equal treatment of labels and other terminators in MI DAG construction.Sergei Larin2013-02-121-1/+1
| | | | | | | MI sched DAG construction allows targets to include terminators into scheduling DAG. Extend this functionality to labels as well. llvm-svn: 174977
* ScheduleDAG: colorize the DOT graph and improve formatting.Andrew Trick2013-01-251-1/+1
| | | | llvm-svn: 173431
* ScheduleDAG: Added isBoundaryNode to conveniently detect a common corner case.Andrew Trick2013-01-251-7/+19
| | | | | | This fixes DAG subtree analysis at the boundary. llvm-svn: 173427
* SchedDFS: Complete support for nested subtrees.Andrew Trick2013-01-251-33/+74
| | | | | | | | | Maintain separate per-node and per-tree book-keeping. Track all instructions above a DAG node including nested subtrees. Seperately track instructions within a subtree. Record subtree parents. llvm-svn: 173426
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-5/+9
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* SchedDFS: Initial support for nested subtrees.Andrew Trick2013-01-251-37/+73
| | | | | | | This is mostly refactoring, along with adding an instruction count within the subtrees and ensuring we only look at data edges. llvm-svn: 173420
* SchedDFS: Refactor and tweak the subtree selection criteria.Andrew Trick2013-01-251-24/+32
| | | | | | | | | | For sanity, create a root when NumDataSuccs >= 4. Splitting large subtrees will no longer be detrimental after my next checkin to handle nested tree. A magic number of 4 is fine because single subtrees seldom rejoin more than this. It makes subtrees easier to visualize and heuristics more sane. llvm-svn: 173399
* Introduce a new data structure, the SparseMultiSet, and changes to the MI ↵Michael Ilseman2013-01-211-45/+33
| | | | | | | | scheduler to use it. A SparseMultiSet adds multiset behavior to SparseSet, while retaining SparseSet's desirable properties. Essentially, SparseMultiSet provides multiset behavior by storing its dense data in doubly linked lists that are inlined into the dense vector. This allows it to provide good data locality as well as vector-like constant-time clear() and fast constant time find(), insert(), and erase(). It also allows SparseMultiSet to have a builtin recycler rather than keeping SparseSet's behavior of always swapping upon removal, which allows it to preserve more iterators. It's often a better alternative to a SparseSet of a growable container or vector-of-vector. llvm-svn: 173064
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* MISched: add dependence to ExitSU to model live-out latency.Andrew Trick2012-12-181-1/+16
| | | | llvm-svn: 170454
* Use GetUnderlyingObjects in mischedHal Finkel2012-12-101-92/+143
| | | | | | | | | | | | | | | | misched used GetUnderlyingObject in order to break false load/store dependencies, and the -enable-aa-sched-mi feature similarly relied on GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis. Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so (especially due to LSR) all of these mechanisms failed for induction-variable-dependent loads and stores inside loops. This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects (which will recurse through phi and select instructions) in misched. Andy reviewed, tested and simplified this patch; Thanks! llvm-svn: 169744
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-9/+9
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick2012-12-011-7/+7
| | | | | | | Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
* misched: Fix the DAG builder to handle an undef operand at ExitSU.Andrew Trick2012-12-011-1/+2
| | | | | | | Assertion failed: (VNI && "No value to read by operand") rdar://12790267. llvm-svn: 169071
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-281-41/+166
| | | | | | | | | | | This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-281-1/+1
| | | | llvm-svn: 168772
* misched: better alias analysis.Andrew Trick2012-11-281-2/+3
| | | | | | | | | | | | | This fixes a hole in the "cheap" alias analysis logic implemented within the DAG builder itself, regardless of whether proper alias analysis is enabled. It now handles this pattern produced by LSR+CodeGenPrepare. %sunkaddr1 = ptrtoint * %obj to i64 %sunkaddr2 = add i64 %sunkaddr1, %lsr.iv %sunkaddr3 = inttoptr i64 %sunkaddr2 to i32* store i32 %v, i32* %sunkaddr3 llvm-svn: 168768
* Fix indeterminism in MI scheduler DAG construction.Sergei Larin2012-11-151-15/+15
| | | | | | | Similarly to several recent fixes throughout the code replace std::map use with the MapVector. Add find() method to the MapVector. llvm-svn: 168051
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-9/+14
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-25/+32
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. llvm-svn: 167435
* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-301-5/+0
| | | | | | | | | | the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation. For inline assembly, however, we need to compute these based on the constraints. Revert r166929 as this is no longer needed, but leave the test case in place. rdar://12033048 and PR13504 llvm-svn: 167040
* This patch addresses a problem with the Post RA scheduler generating anPreston Gurd2012-10-291-0/+5
| | | | | | | | | | | | | | incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could access memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses. This should fix PR13504. llvm-svn: 166929
* Fix typo in comment.Nick Lewycky2012-10-261-1/+1
| | | | llvm-svn: 166750
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-151-0/+93
| | | | llvm-svn: 165950
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-22/+6
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-091-40/+1
| | | | | | This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. llvm-svn: 165563
* misched: remove the unused getSpecialAddressLatency hook.Andrew Trick2012-10-081-40/+7
| | | | llvm-svn: 165418
* misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick2012-10-081-35/+24
| | | | | | SchedModel llvm-svn: 165417
* misched: Make ScheduleDAGInstrs use the TargetSchedule interface.Andrew Trick2012-09-181-16/+14
| | | | llvm-svn: 164153
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | No functional change. llvm-svn: 163339
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-291-1/+1
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Simplify the computeOperandLatency API.Andrew Trick2012-08-231-27/+30
| | | | | | | | | The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. llvm-svn: 162420
* Use the latest MachineRegisterInfo APIs. No functionality.Andrew Trick2012-07-301-1/+1
| | | | llvm-svn: 161010
* Reenable a basic SSA DAG builder optimization.Andrew Trick2012-07-281-5/+4
| | | | | | Jakob fixed ProcessImplicifDefs in r159149. llvm-svn: 160910
* misched: disable SSA check pending PR13112.Andrew Trick2012-06-141-2/+4
| | | | llvm-svn: 158461
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-13/+21
| | | | | | | | | | | For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". llvm-svn: 158380
* Move RegisterPressure.h.Andrew Trick2012-06-061-1/+1
| | | | | | Make it a general utility for use by Targets. llvm-svn: 158097
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-1/+1
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. llvm-svn: 158090
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-61/+18
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-2/+4
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Use LiveRangeQuery in ScheduleDAGInstrs.Jakob Stoklund Olesen2012-05-201-11/+3
| | | | llvm-svn: 157144
* Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick2012-05-151-22/+243
| | | | | | | | | | | | | | | MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! llvm-svn: 156842
* misched: DAG builder must special case earlyclobberAndrew Trick2012-04-241-0/+9
| | | | llvm-svn: 155459
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-241-1/+10
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. llvm-svn: 155456
* New and improved comment.Andrew Trick2012-04-201-1/+1
| | | | llvm-svn: 155229
* SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick2012-04-201-2/+2
| | | | | | | | | | | | | | | | | | | This nicely handles the most common case of virtual register sets, but also handles anticipated cases where we will map pointers to IDs. The goal is not to develop a completely generic SparseSet template. Instead we want to handle the expected uses within llvm without any template antics in the client code. I'm adding a bit of template nastiness here, and some assumption about expected usage in order to make the client code very clean. The expected common uses cases I'm designing for: - integer keys that need to be reindexed, and may map to additional data - densely numbered objects where we want pointer keys because no number->object map exists. llvm-svn: 155227
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