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| author | Andrew Trick <atrick@apple.com> | 2012-06-14 17:48:49 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-14 17:48:49 +0000 |
| commit | 45877fa01179e82d9c2d65138eaaecc3fb0982c8 (patch) | |
| tree | fb53e702115666e0adc51cba4e98889462d3a562 /llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | |
| parent | e993e4cd9b515974bd263a84239e89aa8e6e5903 (diff) | |
| download | bcm5719-llvm-45877fa01179e82d9c2d65138eaaecc3fb0982c8.tar.gz bcm5719-llvm-45877fa01179e82d9c2d65138eaaecc3fb0982c8.zip | |
misched: disable SSA check pending PR13112.
llvm-svn: 158461
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 24b9cd0b45f..110f478f48e 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -413,8 +413,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { // SSA defs do not have output/anti dependencies. // The current operand is a def, so we have at least one. - if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) - return; + // + // FIXME: This optimization is disabled pending PR13112. + //if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) + // return; // Add output dependence to the next nearest def of this vreg. // |
