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path: root/llvm/lib/CodeGen/ScheduleDAG.cpp
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* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-5/+5
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Scheduler diagnostics. Print the register name.Andrew Trick2013-03-011-0/+2
| | | | llvm-svn: 176316
* Instructions schedulers should report correct height/depth.Andrew Trick2013-03-011-2/+2
| | | | | | | | | | | | | We avoided computing DAG height/depth during Node printing because it shouldn't depend on an otherwise valid DAG. But this has become far too annoying for the common case of a valid DAG where we want to see valid values. If doing the computation on-the-fly turns out to be a problem in practice, then I'll add a mode to the diagnostics to only force it when we're likely to have a valid DAG, otherwise explicitly print INVALID instead of bogus numbers. For now, just go for it all the time. llvm-svn: 176314
* Replace loop with std::find.Benjamin Kramer2013-02-161-10/+4
| | | | | | No functionality change. llvm-svn: 175366
* MIsched: Added biasCriticalPath.Andrew Trick2013-01-241-0/+15
| | | | | | | Allow schedulers to order DAG edges by critical path. This makes DFS-based heuristics more stable and effective. llvm-svn: 173317
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-3/+3
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-131-8/+4
| | | | | | | For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. llvm-svn: 167808
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-20/+58
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | No functional change. llvm-svn: 163339
* sched: Avoid trivially redundant DAG edges. Take the one with higher latency.Andrew Trick2012-06-131-3/+20
| | | | llvm-svn: 158379
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-15/+7
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-17/+0
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-9/+4
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* Don't print out pointer values in SUnit::dump().Jakob Stoklund Olesen2012-02-171-5/+3
| | | | llvm-svn: 150842
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-141-1/+1
| | | | llvm-svn: 148174
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Make a bunch of symbols private.Benjamin Kramer2011-08-191-1/+1
| | | | llvm-svn: 138025
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-1/+1
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-151-0/+12
| | | | | | Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-2/+2
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-2/+4
| | | | | | | | | | | | | | | precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. llvm-svn: 124853
* Fix a few cases where the scheduler is not checking for phys reg copies. The ↵Andrew Trick2010-12-241-1/+1
| | | | | | scheduling node may have a NULL DAG node, yuck. llvm-svn: 122544
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* reduce indentation, no functionality change.Chris Lattner2010-12-201-1/+1
| | | | llvm-svn: 122208
* Remove trailing whitespace, no functionality changes.John Mosby2010-06-301-19/+18
| | | | llvm-svn: 107244
* Remove unused member variable.Zhongxing Xu2010-05-171-1/+0
| | | | llvm-svn: 103936
* Delete an unused member variable.Dan Gohman2010-04-131-1/+0
| | | | llvm-svn: 101143
* Change errs() to dbgs().David Greene2010-01-051-40/+40
| | | | llvm-svn: 92585
* Remove some old experimental code that is no longer needed. Remove ↵David Goodwin2009-11-201-14/+6
| | | | | | additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. llvm-svn: 89471
* Rename registers to break output dependencies in addition to anti-dependencies.David Goodwin2009-11-121-2/+8
| | | | llvm-svn: 87015
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-031-7/+9
| | | | | | registers that should be renamed. llvm-svn: 85939
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-301-4/+16
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* Convert DOUT to DEBUG(errs()...).Bill Wendling2009-08-221-3/+5
| | | | llvm-svn: 79760
* Add some debug output.David Goodwin2009-08-111-0/+2
| | | | llvm-svn: 78687
* Move to raw_ostream.Daniel Dunbar2009-07-241-36/+37
| | | | llvm-svn: 76963
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-11/+6
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Use iterators to iterate through the Preds array instead ofDan Gohman2009-02-111-2/+3
| | | | | | | an index. This code is on the hot-path because the current way SDep edges are uniqued has quadratic complexity. llvm-svn: 64262
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-1/+4
| | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. llvm-svn: 64254
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-1/+8
| | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. llvm-svn: 62366
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-151-0/+3
| | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. llvm-svn: 62284
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-9/+13
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Avoid referring to edge D after the Succs or Preds arrays haveDan Gohman2009-01-131-3/+3
| | | | | | | been modified, to avoid trouble in the (unlikely) scenario that D is a reference to an element in one of those arrays. llvm-svn: 62173
* Don't call setDepthDirty/setHeightDirty when adding an edgeDan Gohman2009-01-051-4/+8
| | | | | | with latency 0, since it doesn't affect the depth or height. llvm-svn: 61762
* Minor code simplifications.Dan Gohman2008-12-231-6/+6
| | | | llvm-svn: 61371
* Optimize setDepthDirty and setHeightDirty a little, as they showedDan Gohman2008-12-221-10/+16
| | | | | | up on a profile. llvm-svn: 61344
* Use SmallVector's pop_back_val.Dan Gohman2008-12-201-4/+2
| | | | llvm-svn: 61277
* Use the correct Preds and Succs lists in setHeightDirty()Dan Gohman2008-12-201-4/+4
| | | | | | and setDepthDirty(), respectively. This fixes PR3241. llvm-svn: 61276
* Use getDepth() and getHeight() instead of accessing theDan Gohman2008-12-171-2/+2
| | | | | | | Depth and Height members directly, as they may not be current. llvm-svn: 61121
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