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path: root/llvm/lib/CodeGen/RegAllocGreedy.cpp
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* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* Mark all library options as hidden.Zachary Turner2017-12-011-4/+5
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-15/+15
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-19/+19
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-221-9/+347
* [NFC] Convert OptimizationRemarkEmitter old emit() calls to new closureVivek Pandya2017-10-111-11/+14
* Rename OptimizationDiagnosticInfo.* to OptimizationRemarkEmitter.*Adam Nemet2017-10-091-1/+1
* [RegAllocGreedy]: Allow recoloring of done register if it's non-tiedMikael Holmen2017-09-281-2/+14
* [RegAllocGreedy] Fix spelling error, "inteference" -> "interference", NFCMikael Holmen2017-09-271-3/+3
* Recommit "[RegAlloc] Make sure live-ranges reflect the state of the IR whenJonas Paulsson2017-09-151-1/+4
* Revert "[RegAlloc] Make sure live-ranges reflect the state of the IR when rem...Jonas Paulsson2017-09-071-4/+1
* [RegAlloc] Make sure live-ranges reflect the state of the IR when removing themQuentin Colombet2017-08-211-1/+4
* fix typos in comments and error messages; NFCHiroshi Inoue2017-07-101-1/+1
* fix trivial typo, NFCHiroshi Inoue2017-06-291-1/+1
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-06-061-37/+59
* BitVector: add iterators for set bitsFrancis Visoiu Mistrih2017-05-171-7/+4
* RegAllocGreedy: Follow-up to r296722Matthias Braun2017-03-031-1/+5
* LIU:::Query: Query LiveRange instead of LiveInterval; NFCMatthias Braun2017-03-011-1/+1
* New OptimizationRemarkEmitter pass for MIRAdam Nemet2017-01-251-0/+84
* Timer: Track name and description.Matthias Braun2016-11-181-4/+8
* [RegAllocGreedy] Record missed hint for late recoloring.Quentin Colombet2016-11-161-0/+3
* RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard2016-11-141-13/+18
* [RegAllocGreedy] Another fix about NewVRegs for last chance recoloring after ...Wei Mi2016-11-081-8/+5
* [RAGreedy] Empty live-ranges always succeed in last chance recoloring.Quentin Colombet2016-10-131-1/+12
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-10-111-6/+8
* Turn cl::values() (for enum) from a vararg function to using C++ variadic tem...Mehdi Amini2016-10-081-2/+1
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
* Revert "[RegAllocGreedy] Attempt to split unspillable live intervals"Dylan McKay2016-09-301-8/+6
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-09-301-6/+8
* [RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.Quentin Colombet2016-09-161-2/+22
* [RegAllocGreedy] Fix an assertion and condition when last chance recoloring i...Quentin Colombet2016-09-161-2/+3
* MachineFunction: Introduce NoPHIs propertyMatthias Braun2016-08-231-0/+5
* Allow dead insts to be kept in DeadRemat only when they are rematerializable.Wei Mi2016-07-081-1/+3
* Recommit r265547, and r265610,r265639,r265657 on top of it, plusWei Mi2016-04-131-14/+17
* Revert r265547 "Recommit r265309 after fixed an invalid memory reference bug ...Hans Wennborg2016-04-081-17/+14
* Recommit r265309 after fixed an invalid memory reference bug happenedWei Mi2016-04-061-14/+17
* Revert r265309 and r265312 because they caused some errors I need to investig...Wei Mi2016-04-041-17/+14
* Replace analyzeSiblingValues with new algorithm to fix its compileWei Mi2016-04-041-14/+17
* Add MachineVerifier check for AllVRegsAllocated MachineFunctionPropertyDerek Schuff2016-03-291-4/+0
* Introduce MachineFunctionProperties and the AllVRegsAllocated propertyDerek Schuff2016-03-281-0/+4
* Remove uses of builtin comma operator.Richard Trieu2016-02-181-12/+20
* [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatibleChandler Carruth2015-09-091-2/+2
* Trace copies when checking for rematerializability in spill weight calculationRobert Lougher2015-08-101-1/+1
* [RAGreedy] Add an experimental deferred spilling feature.Quentin Colombet2015-07-171-6/+37
* TargetRegisterInfo: Provide a way to check assigned registers in getRegAlloca...Matthias Braun2015-07-151-2/+2
* RAGreedy: Keep track of allocated PhysRegs internallyMatthias Braun2015-07-141-18/+24
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-311-3/+4
* RegAllocGreedy: Improve live interval order in ReverseLocal modeMatthias Braun2015-03-311-1/+1
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