| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
llvm-svn: 10728
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
llvm-svn: 10461
|
|
|
|
| |
llvm-svn: 9903
|
|
|
|
|
|
|
| |
* Doxygen-ify comments
* Make code layout more consistent
llvm-svn: 9431
|
|
|
|
|
|
| |
Header files will be on the way.
llvm-svn: 9298
|
|
|
|
| |
llvm-svn: 8297
|
|
|
|
|
|
| |
adding std:: namespace qualifiers
llvm-svn: 8295
|
|
|
|
|
|
|
|
|
|
|
| |
info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
llvm-svn: 7329
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341
|
|
|
|
| |
llvm-svn: 5314
|
|
|
|
| |
llvm-svn: 5307
|
|
|
|
| |
llvm-svn: 5272
|
|
|
|
| |
llvm-svn: 4382
|
|
|
|
| |
llvm-svn: 4380
|
|
|
|
| |
llvm-svn: 4344
|
|
|
|
|
|
| |
MachineOperand::getType()
llvm-svn: 4331
|
|
|
|
|
|
| |
llvm/Target/MachineInstrInfo.h
llvm-svn: 4327
|
|
|
|
| |
llvm-svn: 4323
|
|
|
|
| |
llvm-svn: 4317
|
|
|
|
|
|
|
| |
created here, simply by handling all implicit operands (which should
have been done anyway).
llvm-svn: 3969
|
|
|
|
|
|
|
|
| |
than #available regs, compute the sum excluding duplicates and if that
is less than #regs, go ahead and coalesce.
Add method IGNode::getCombinedDegree to count excluding duplicates.
llvm-svn: 3842
|
|
|
|
|
|
| |
debug output.
llvm-svn: 3724
|
|
|
|
|
|
|
| |
because operands may be modified directly to set register.
Also, class MachineCodeForBasicBlock is now an annotation on BasicBlock.
llvm-svn: 2832
|
|
|
|
|
|
| |
For details, See: docs/2002-06-25-MegaPatchInfo.txt
llvm-svn: 2779
|
|
|
|
| |
llvm-svn: 2397
|
|
|
|
|
|
|
| |
class. The Method class is obsolete (renamed) and all references to it
are being converted over to Function.
llvm-svn: 2144
|
|
|
|
|
|
|
| |
Method::inst_* is now in llvm/Support/InstIterator.h
GraphTraits specializations for BasicBlock and Methods are now in llvm/Support/CFG.h
llvm-svn: 1746
|
|
|
|
| |
llvm-svn: 1720
|
|
|
|
|
|
| |
* Removal dependencies on Type.h & remove uses of getTypeID()
llvm-svn: 1718
|
|
|
|
| |
llvm-svn: 1716
|
|
|
|
|
|
|
|
|
|
| |
function in the one .cpp file that uses it. Use ValueSet's instead.
* Prepare to delete LiveVarSet.h & LiveVarSet.cpp
* Eliminate the ValueSet class, making all old member functions into global
templates that will eventually be moved to Support.
* Eliminate some irrelevant const's
llvm-svn: 1712
|
|
|
|
|
|
| |
* Introduce RAV to allow stream I/O instead of using printValue
llvm-svn: 1710
|
|
|
|
|
|
|
| |
* ValueSet interface converted from add/remove to insert/erase
* Minor cleanups
llvm-svn: 1689
|
|
|
|
| |
llvm-svn: 1675
|
|
|
|
| |
llvm-svn: 1503
|
|
|
|
|
|
| |
Added correct spill candidate selection logic.
llvm-svn: 1493
|
|
|
|
|
|
|
| |
Renamed op_const_iterator -> const_op_iterator
Renamed PointerType::getValueType() -> PointerType::getElementType()
llvm-svn: 1408
|
|
|
|
|
|
| |
regClass since FP class has two reg Types.
llvm-svn: 1236
|
|
|
|
| |
llvm-svn: 916
|
|
|
|
| |
llvm-svn: 847
|
|
|
|
|
|
| |
generation
llvm-svn: 840
|
|
|
|
|
|
| |
Changed added instr to a deque (from a vector)
llvm-svn: 831
|
|
|
|
| |
llvm-svn: 729
|
|
|
|
| |
llvm-svn: 670
|
|
|
|
|
|
| |
* Spell PhyRegAlloc right.
llvm-svn: 645
|
|
|
|
| |
llvm-svn: 631
|
|
|
|
| |
llvm-svn: 590
|
|
llvm-svn: 580
|