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path: root/llvm/lib/CodeGen/PostRASchedulerList.cpp
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* The subtarget is cached on the MachineFunction. Access it directly.Eric Christopher2015-01-271-3/+1
| | | | llvm-svn: 227173
* Whitespace.NAKAMURA Takumi2014-10-291-5/+5
| | | | llvm-svn: 220857
* Grab the subtarget and subtarget dependent variables off ofEric Christopher2014-10-141-4/+2
| | | | | | MachineFunction rather than TargetMachine. llvm-svn: 219670
* Cleanup: Delete seemingly unused reference to MachineDominatorTree from ↵Alexey Samsonov2014-08-201-11/+10
| | | | | | ScheduleDAGInstrs. llvm-svn: 216124
* Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov2014-08-201-1/+1
| | | | | | | | | Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-1/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+5
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-3/+20
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-10/+10
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-311-0/+3
| | | | | | | pass normally runs at optimization level None, or is part of the register allocation pipeline. llvm-svn: 205228
* remove a bunch of unused private methodsNuno Lopes2014-03-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-10/+10
| | | | | | class. llvm-svn: 203220
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+3
| | | | | | Remove the old functions. llvm-svn: 202636
* Move the PostRA scheduler's fixupKills function for reuse.Andrew Trick2013-12-281-160/+3
| | | | llvm-svn: 198121
* Add two additional hazard recognizer functionsHal Finkel2013-12-111-7/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds two additional functions to the hazard recognizer interface. These are optional (in the sense that the default implementations preserve the current behavior), and used by the post-RA scheduler. Upcoming commits will use this functionality in order to improve dispatch-group formation on the POWER7 and related cores. Dispatch groups are an odd construct: sometimes we need to insert nops to force a new one to start (for performance reasons), and some instructions need to appear in certain positions within a group, but the groups are not fundamentally cycle based (they can contain instructions with data dependencies with non-trivial latencies). Motivation: unsigned PreEmitNoops(SUnit *) - Used to force the post-RA scheduler to insert nops to force a new dispatch group to begin. We already have a NoopHazard, and this is also still needed. However, NoopHazard only causes a nop to be inserted if there are no other available instructions, and so is not always sufficient. The number of nops to insert depends on state that only the hazard recognizer has, so a general callback is necessary. bool ShouldPreferAnother(SUnit *) - Used to avoid scheduling instructions that would start a new dispatch group when others are available that could be part of the current dispatch group. In this case, we don't want to issue nops, because the non-preferred instruction will implicitly start a new dispatch group regardless. Although the motivation for these functions is driven by the PowerPC backend, they are completely general. llvm-svn: 197084
* After PostRA scheduling, don't set kill flags on undef operands.Andrew Trick2013-10-161-2/+2
| | | | | | This should fix the ATOM buildbot failing on break-avx-dep.ll. llvm-svn: 192824
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr ↵Andrew Trick2013-08-231-7/+18
| | | | | | | | | count. This fixes a pathological compile time problem with very large blocks and lots of scheduling boundaries. llvm-svn: 189116
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-10/+8
| | | | llvm-svn: 182531
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-19/+5
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen2012-12-201-5/+3
| | | | | | This automatically passes a context pointer to MI->addOperand(). llvm-svn: 170711
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-11/+11
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-131-1/+1
| | | | | | | For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. llvm-svn: 167808
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-7/+7
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-3/+2
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
| | | | | | No functional change. llvm-svn: 163339
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-1/+0
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. llvm-svn: 158090
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-19/+13
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-091-7/+7
| | | | | | not private. llvm-svn: 152382
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-1/+1
| | | | | | implement their own MachineScheduler. llvm-svn: 152261
* misched prep: rename InsertPos to End.Andrew Trick2012-03-071-8/+8
| | | | | | ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-17/+17
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-12/+38
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-0/+36
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+18
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-2/+8
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-6/+6
| | | | | | static data size. llvm-svn: 152016
* BitVectorize loop.Benjamin Kramer2012-02-231-3/+1
| | | | llvm-svn: 151274
* post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored ↵Benjamin Kramer2012-02-231-28/+22
| | | | | | | | two meaningful states. Rename it to LiveRegs to make it more clear what's stored inside. llvm-svn: 151273
* post-ra-sched: Replace a std::set of regs with a bitvector.Benjamin Kramer2012-02-231-5/+4
| | | | | | | | | Assuming that a single std::set node adds 3 control words, a bitvector can store (3*8+4)*8=224 registers in the allocated memory of a single element in the std::set (x86_64). Also we don't have to call malloc for every register added. llvm-svn: 151269
* Make calls scheduling boundaries post-ra.Jakob Stoklund Olesen2012-02-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before register allocation, instructions can be moved across calls in order to reduce register pressure. After register allocation, we don't gain a lot by moving callee-saved defs across calls. In fact, since the scheduler doesn't have a good idea how registers are used in the callee, it can't really make good scheduling decisions. This changes the schedule in two ways: 1. Latencies to call uses and defs are no longer accounted for, causing some random shuffling around calls. This isn't really a problem since those uses and defs are inaccurate proxies for what happens inside the callee. They don't represent registers used by the call instruction itself. 2. Instructions are no longer moved across calls. This didn't happen very often, and the scheduling decision was made on dubious information anyway. As with any scheduling change, benchmark numbers shift around a bit, but there is no positive or negative trend from this change. This makes the post-ra scheduler 5% faster for ARM targets. The secret motivation for this patch is the introduction of register mask operands representing call clobbers. The most efficient way of handling regmasks in ScheduleDAGInstrs is to model them as barriers for physreg live ranges, but not for virtreg live ranges. That's fine pre-ra, but post-ra it would have the same effect as this patch. llvm-svn: 151265
* Handle regmasks in FixupKills.Jakob Stoklund Olesen2012-02-231-0/+4
| | | | llvm-svn: 151226
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-3/+3
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-12/+5
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-081-6/+8
| | | | llvm-svn: 150096
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-141-1/+1
| | | | llvm-svn: 148172
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