summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/Passes.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson2012-07-021-3/+15
| | | | | | | | | | | | | | | | | This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. llvm-svn: 159570
* Move assertion with TargetPassConfig's Initialized flag.Bob Wilson2012-07-021-2/+2
| | | | llvm-svn: 159569
* Consistently use AnalysisID types in TargetPassConfig.Bob Wilson2012-07-021-61/+59
| | | | | | | This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. llvm-svn: 159568
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-20/+53
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen2012-06-261-1/+5
| | | | | | | | Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. llvm-svn: 159209
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-251-6/+2
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. llvm-svn: 159149
* Reintroduce VirtRegRewriter.Jakob Stoklund Olesen2012-06-081-0/+4
| | | | | | | | | | | | | | | | | | OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
* Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>Bob Wilson2012-05-301-0/+42
| | | | | | | | | | Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! llvm-svn: 157655
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-21/+21
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-161-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
* Enable machine code verification in the entire code generator.Jakob Stoklund Olesen2012-03-281-8/+3
| | | | | | | | | | Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. llvm-svn: 153615
* Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | | | | | | | The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. llvm-svn: 153614
* Also verify after ExpandPostRAPseudos.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | llvm-svn: 153599
* Enable machine code verification after the late machine optimization passes.Jakob Stoklund Olesen2012-03-281-3/+3
| | | | | | | Branch folding invalidates liveness and disables liveness verification on some targets. llvm-svn: 153597
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-1/+2
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. llvm-svn: 152700
* Fix machine-cp by having it to check sub-register indicies. e.g.Evan Cheng2012-02-201-1/+1
| | | | | | | | | | | | ecx = mov eax al = mov ch The second copy is not a nop because the sub-indices of ecx,ch is not the same of that of eax/al. Re-enabled machine-cp. PR11940 llvm-svn: 151002
* Disable machine copy propagation for now. It's known to be buggy (PR11940) ↵Benjamin Kramer2012-02-161-1/+1
| | | | | | and introduces subtle miscompiles in many places. llvm-svn: 150703
* Revert r150565 again. Appears to be a stage2 failure with dragonegg.Andrew Trick2012-02-151-6/+8
| | | | | | I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it. llvm-svn: 150568
* Reapply r150565 with the typo fix properly merged.Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150567
* reverting r150565. Premature push.Andrew Trick2012-02-151-6/+8
| | | | llvm-svn: 150566
* Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150565
* Allow CodeGen (llc) command line options to work as expected.Andrew Trick2012-02-151-52/+114
| | | | | | | | | | | | | | | | | | | | | | | | The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes. A target has two ways of overriding standard passes: 1) Redefine the pass pipeline (override TargetPassConfig::add%Stage) 2) Replace or suppress individiual passes with TargetPassConfig::substitutePass. In both cases, the command line options associated with the pass override the target default. For example, say a target wants to disable machine instruction scheduling by default: - The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods. - Without any llc options, no scheduler is run. - With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing. Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day... I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well. llvm-svn: 150563
* Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ↵Andrew Trick2012-02-151-6/+42
| | | | | | override specific passes. llvm-svn: 150562
* Add TargetPassConfig hooks for scheduling/bundling.Andrew Trick2012-02-111-3/+41
| | | | | | | | | In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. llvm-svn: 150298
* comment grammarAndrew Trick2012-02-101-1/+1
| | | | llvm-svn: 150233
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-36/+113
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* Improve TargetPassConfig. No intended functionality.Andrew Trick2012-02-091-98/+149
| | | | | | | Split CodeGen into stages. Distinguish between optimization and correctness. llvm-svn: 150122
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-20/+20
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: MachineLICM.Andrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150099
* Move pass configuration out of pass constructors: StackSlotColoring.Andrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150097
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-081-1/+1
| | | | llvm-svn: 150096
* Move pass configuration out of pass constructors: BranchFolderPassAndrew Trick2012-02-081-1/+3
| | | | llvm-svn: 150095
* Added TargetPassConfig::setOptAndrew Trick2012-02-081-1/+10
| | | | llvm-svn: 150093
* Added Pass::createPass(ID) to handle pass configuration by IDAndrew Trick2012-02-081-2/+6
| | | | llvm-svn: 150092
* Move pass configuration out of pass constructors: TailDuplicate::PreRegAllocAndrew Trick2012-02-081-2/+2
| | | | llvm-svn: 150091
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-041-74/+16
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Move TargetPassConfig implementation into Passes.cppAndrew Trick2012-02-041-1/+310
| | | | llvm-svn: 149753
* Make TargetPassConfig an ImmutablePass so CodeGenPasses can query optionsAndrew Trick2012-02-041-0/+34
| | | | llvm-svn: 149752
* Delete the linear scan register allocator.Jakob Stoklund Olesen2011-11-121-5/+0
| | | | | | | | | RegAllocGreedy has been the default for six months now. Deleting RegAllocLinearScan makes it possible to also delete VirtRegRewriter and clean up the spiller code. llvm-svn: 144475
* Update comment.Jakob Stoklund Olesen2011-04-301-2/+2
| | | | llvm-svn: 130582
* Use a greedy algorithm for allocating registers.Jakob Stoklund Olesen2011-04-301-3/+3
| | | | llvm-svn: 130568
* Force the greedy register allocator to be linked alongside linear scan.Jakob Stoklund Olesen2011-04-191-0/+5
| | | | | | This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'. llvm-svn: 129764
* Use the fast register allocator by default for -O0 builds.Jakob Stoklund Olesen2010-06-031-1/+1
| | | | | | This affects both llvm-gcc and clang. llvm-svn: 105372
* Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen2010-05-271-6/+20
| | | | | | | | | optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. llvm-svn: 104904
* Uniformize the way these options are printed. Requested byDuncan Sands2010-02-181-1/+1
| | | | | | Russell Wallace. llvm-svn: 96580
* Clean up the use of static and anonymous namespaces. This turned upDan Gohman2008-05-131-8/+5
| | | | | | | several things that were neither in an anonymous namespace nor static but not intended to be global. llvm-svn: 51017
* Make several variable declarations static.Dan Gohman2008-05-061-0/+1
| | | | llvm-svn: 50696
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* *** empty log message ***Bill Wendling2006-11-161-1/+0
| | | | llvm-svn: 31789
* Work around a bug in gcc 3.3.5, reported by a userChris Lattner2006-08-031-1/+1
| | | | llvm-svn: 29489
OpenPOWER on IntegriCloud