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path: root/llvm/lib/CodeGen/Passes.cpp
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* Don't leak passes if added outside of the area determined by Started/Stopped ↵Benjamin Kramer2013-08-051-0/+2
| | | | | | flags. llvm-svn: 187722
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-1/+1
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-2/+2
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184352
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-3/+3
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* The DWARF EH pass doesn't need the TargetMachine, only the ↵Bill Wendling2013-05-201-1/+1
| | | | | | TargetLoweringBase like the other EH passes. llvm-svn: 182321
* Add braces around || in && to pacify GCC.Benjamin Kramer2013-04-111-4/+4
| | | | llvm-svn: 179275
* Generalize the PassConfig API and remove addFinalizeRegAlloc().Andrew Trick2013-04-101-36/+50
| | | | | | | | | | The target hooks are getting out of hand. What does it mean to run before or after regalloc anyway? Allowing either Pass* or AnalysisID pass identification should make it much easier for targets to use the substitutePass and insertPass APIs, and create less need for badly named target hooks. llvm-svn: 179140
* Remove the old CodePlacementOpt pass.Benjamin Kramer2013-03-291-18/+3
| | | | | | It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. llvm-svn: 178349
* Remove unused #includes.Bill Wendling2013-03-051-1/+0
| | | | llvm-svn: 176467
* Fix a typo.Cameron Zwarich2013-02-101-1/+1
| | | | llvm-svn: 174830
* Provide a place for targets to insert ILP optimization passes.Jakob Stoklund Olesen2013-01-171-4/+6
| | | | | | | | | | | | | | Move the early if-conversion pass into this group. ILP optimizations usually need to find the right balance between register pressure and ILP using the MachineTraceMetrics analysis to identify critical paths and estimate other costs. Such passes should run together so they can share dominator tree and loop info analyses. Besides if-conversion, future passes to run here here could include expression height reduction and ARM's MLxExpansion pass. llvm-svn: 172687
* Switch the SCEV expander and LoopStrengthReduce to useChandler Carruth2013-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetTransformInfo rather than TargetLowering, removing one of the primary instances of the layering violation of Transforms depending directly on Target. This is a really big deal because LSR used to be a "special" pass that could only be tested fully using llc and by looking at the full output of it. It also couldn't run with any other loop passes because it had to be created by the backend. No longer is this true. LSR is now just a normal pass and we should probably lift the creation of LSR out of lib/CodeGen/Passes.cpp and into the PassManagerBuilder. =] I've not done this, or updated all of the tests to use opt and a triple, because I suspect someone more familiar with LSR would do a better job. This change should be essentially without functional impact for normal compilations, and only change behvaior of targetless compilations. The conversion required changing all of the LSR code to refer to the TTI interfaces, which fortunately are very similar to TargetLowering's interfaces. However, it also allowed us to *always* expect to have some implementation around. I've pushed that simplification through the pass, and leveraged it to simplify code somewhat. It required some test updates for one of two things: either we used to skip some checks altogether but now we get the default "no" answer for them, or we used to have no information about the target and now we do have some. I've also started the process of removing AddrMode, as the TTI interface doesn't use it any longer. In some cases this simplifies code, and in others it adds some complexity, but I think it's not a bad tradeoff even there. Subsequent patches will try to clean this up even further and use other (more appropriate) abstractions. Yet again, almost all of the formatting changes brought to you by clang-format. =] llvm-svn: 171735
* Add targets to skip running the GC passes.Evan Cheng2012-12-211-3/+10
| | | | llvm-svn: 170836
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-7/+7
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Replace r168930 with a more reasonable patch.Bill Wendling2012-11-301-3/+7
| | | | | | | | | | | The original patch removed a bunch of code that the SjLjEHPrepare pass placed into the entry block if all of the landing pads were removed during the CodeGenPrepare class. The more natural way of doing things is to run the CGP *before* we run the SjLjEHPrepare pass. Make it so! llvm-svn: 169044
* Move else onto line with preceding closing brace.Craig Topper2012-11-191-2/+1
| | | | llvm-svn: 168294
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-1/+4
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* revert r166264 because the LTO build is still failingNadav Rotem2012-10-191-2/+2
| | | | llvm-svn: 166340
* recommit the patch that makes LSR and LowerInvoke use the TargetTransform ↵Nadav Rotem2012-10-191-2/+2
| | | | | | interface. llvm-svn: 166264
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-181-2/+2
| | | | | | | | | | | The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 llvm-svn: 166168
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-101-2/+2
| | | | | | information. llvm-svn: 165665
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-3/+3
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+4
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-051-2/+2
| | | | llvm-svn: 163258
* Add a verification pass after ExpandISelPseudos.Jakob Stoklund Olesen2012-08-201-1/+2
| | | | | | | This pass often has weird CFG hacks and hand-written MI building code that can go wrong in many ways. llvm-svn: 162224
* Add an experimental -early-live-intervals option.Jakob Stoklund Olesen2012-08-031-0/+9
| | | | | | | | | | This option runs LiveIntervals before TwoAddressInstructionPass which will eventually learn to exploit and update the analysis. Eventually, LiveIntervals will run before PHIElimination, and we can get rid of LiveVariables. llvm-svn: 161270
* Make sure -print-machineinstrs applies to the first pass as well.Jakob Stoklund Olesen2012-07-041-3/+3
| | | | llvm-svn: 159720
* Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen2012-07-041-0/+9
| | | | | | | | | | | | | This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. llvm-svn: 159694
* All glory to address sanitizer. ;]Chandler Carruth2012-07-021-2/+8
| | | | | | | | | | | | It appears to have caught a use-after-free introduced as by r159567 and/or friends which call 'addPass' from many more places. The bug in 'addPass' doesn't appear to be new, and was spotted by inspection when ASan shown a bright light of a stacktrace at these functions. Hopefully this will fix the ASan failure -- I have no test case other than running an ASan-built clang over the test suite. llvm-svn: 159614
* Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson2012-07-021-3/+15
| | | | | | | | | | | | | | | | | This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. llvm-svn: 159570
* Move assertion with TargetPassConfig's Initialized flag.Bob Wilson2012-07-021-2/+2
| | | | llvm-svn: 159569
* Consistently use AnalysisID types in TargetPassConfig.Bob Wilson2012-07-021-61/+59
| | | | | | | This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. llvm-svn: 159568
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-20/+53
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen2012-06-261-1/+5
| | | | | | | | Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. llvm-svn: 159209
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-251-6/+2
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. llvm-svn: 159149
* Reintroduce VirtRegRewriter.Jakob Stoklund Olesen2012-06-081-0/+4
| | | | | | | | | | | | | | | | | | OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
* Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>Bob Wilson2012-05-301-0/+42
| | | | | | | | | | Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! llvm-svn: 157655
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-21/+21
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-161-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
* Enable machine code verification in the entire code generator.Jakob Stoklund Olesen2012-03-281-8/+3
| | | | | | | | | | Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. llvm-svn: 153615
* Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | | | | | | | The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. llvm-svn: 153614
* Also verify after ExpandPostRAPseudos.Jakob Stoklund Olesen2012-03-281-1/+1
| | | | llvm-svn: 153599
* Enable machine code verification after the late machine optimization passes.Jakob Stoklund Olesen2012-03-281-3/+3
| | | | | | | Branch folding invalidates liveness and disables liveness verification on some targets. llvm-svn: 153597
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-1/+2
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. llvm-svn: 152700
* Fix machine-cp by having it to check sub-register indicies. e.g.Evan Cheng2012-02-201-1/+1
| | | | | | | | | | | | ecx = mov eax al = mov ch The second copy is not a nop because the sub-indices of ecx,ch is not the same of that of eax/al. Re-enabled machine-cp. PR11940 llvm-svn: 151002
* Disable machine copy propagation for now. It's known to be buggy (PR11940) ↵Benjamin Kramer2012-02-161-1/+1
| | | | | | and introduces subtle miscompiles in many places. llvm-svn: 150703
* Revert r150565 again. Appears to be a stage2 failure with dragonegg.Andrew Trick2012-02-151-6/+8
| | | | | | I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it. llvm-svn: 150568
* Reapply r150565 with the typo fix properly merged.Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150567
* reverting r150565. Premature push.Andrew Trick2012-02-151-6/+8
| | | | llvm-svn: 150566
* Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150565
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