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* Delete some dead code.Rafael Espindola2016-06-211-5/+0
| | | | | | Found by gcc 6. llvm-svn: 273303
* MachineVerifier: subregs so not require defs/valnos on every pathMatthias Braun2016-05-201-2/+3
| | | | | | | | | | | It is fine for subregister ranges to be undefined on some CFG paths as we may have a "vregX:other_subreg<read-undef> =" def on that path. We do not (and should not) have live segments for the subregister ranges. The MachineVerifier should not complain about this. This is a slight variant of http://llvm.org/PR27705 llvm-svn: 270290
* MachineVerifier: Fix error reporting.Matthias Braun2016-05-111-4/+10
| | | | | | | Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
* [MachineVerifier] Teach how to check some of the properties of genericQuentin Colombet2016-04-081-1/+24
| | | | | | | | | | | | | | virtual registers. Generic virtual registers: - May not have a register class - May not have a register bank - If they do not have a register class they must have a size - If they have a register bank, the size of the register bank must be greater or equal to the size of the virtual register (basically check that the virtual register will fit into that register class) llvm-svn: 265798
* MachineVerifier: On dead-def live segments, check that corresponding machine ↵Matthias Braun2016-03-291-3/+18
| | | | | | operand has a dead flag llvm-svn: 264769
* Add MachineVerifier check for AllVRegsAllocated MachineFunctionPropertyDerek Schuff2016-03-291-0/+16
| | | | | | | | | | | | | | | | | Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
* WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | | | Update APIs in MachineInstrBundle.h to take and return MachineInstr& instead of MachineInstr* when the instruction cannot be null. Besides being a nice cleanup, this is tacking toward a fix for PR26753. llvm-svn: 262141
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-271-11/+11
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-2/+2
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* ADT: Remove == and != comparisons between ilist iterators and pointersDuncan P. N. Exon Smith2016-02-211-1/+1
| | | | | | | | | | | | | | I missed == and != when I removed implicit conversions between iterators and pointers in r252380 since they were defined outside ilist_iterator. Since they depend on getNodePtrUnchecked(), they indirectly rely on UB. This commit removes all uses of these operators. (I'll delete the operators themselves in a separate commit so that it can be easily reverted if necessary.) There should be NFC here. llvm-svn: 261498
* MachineVerifier: Add parameter to choose if MachineFunction::verify() abortsMatthias Braun2016-02-151-10/+13
| | | | | | | The abort on error behaviour is unpractical for debugger and unittest usage. llvm-svn: 260904
* MachineVerifier: Check that defs/uses are live in subregisters as well.Matthias Braun2016-02-021-52/+141
| | | | llvm-svn: 259552
* MachineVerifier: Use report_context() instead of ad-hoc messages.Matthias Braun2016-02-021-10/+32
| | | | llvm-svn: 259457
* LiveInterval: A LiveRange is enough for ConnectedVNInfoEqClasses::Classify()Matthias Braun2016-01-081-1/+1
| | | | llvm-svn: 257129
* Move EH-specific helper functions to a more appropriate placeDavid Majnemer2015-12-021-1/+1
| | | | | | No functionality change is intended. llvm-svn: 254562
* MachineVerifier: Streamline live interval related error reportingMatthias Braun2015-11-091-90/+93
| | | | | | | | | Simply perform additional report_context() calls after a report() instead of adding more and more overloaded variations of report(). Also improve several instances where information was output in an ad-hoc way probably because no matching report() overload was available. llvm-svn: 252552
* MachineVerifier: Add missing linebreakMatthias Braun2015-11-091-0/+1
| | | | | | | MachineInstr::print() with SkipOppers==true does not produce a linebreak, so we have to do that in MachineVerifier::report(). llvm-svn: 252551
* MachineVerifier: MI::print has no TargetMachine overloadMatthias Braun2015-11-091-1/+1
| | | | | | | The code was passing a target machine pointer which degraded to a true operand to SkipOppers. llvm-svn: 252550
* MachineVerifier: print list of live intervals if availableMatthias Braun2015-11-091-1/+4
| | | | llvm-svn: 252549
* [WinEH] Tweak funclet prologue/epilogue insertion to pass verifierReid Kleckner2015-11-091-1/+4
| | | | | | | | | | For some reason we'd never run MachineVerifier on WinEH code, and you explicitly have to ask for it with llc. I added it to a few test cases to get some coverage. Fixes PR25461. llvm-svn: 252512
* [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.Jonas Paulsson2015-10-291-6/+25
| | | | | | | | | | | | | Since the verifier will give false reports if it incorrectly thinks MI is loading or storing using an FI, it is necessary to scan memoperands and find out how the FI is used in the instruction. This should be relatively rare. Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag. Reviewed by Quentin Colombet. llvm-svn: 251620
* Let MachineVerifier be aware of mem-to-mem instructions.Jonas Paulsson2015-10-211-2/+8
| | | | | | | | | | | | | | | A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
* CodeGen: Continue removing ilist iterator implicit conversionsDuncan P. N. Exon Smith2015-10-091-20/+25
| | | | llvm-svn: 249884
* TargetRegisterInfo: Introduce PrintLaneMask.Matthias Braun2015-09-251-3/+2
| | | | | | | This makes it more convenient to print lane masks and lead to more uniform printing. llvm-svn: 248624
* TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where ↵Matthias Braun2015-09-251-10/+11
| | | | | | apropriate; NFC llvm-svn: 248623
* Save LaneMask with livein registersMatthias Braun2015-09-091-5/+5
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* MachineVerifier: Check that SlotIndex MBBIndexList is sorted.Matthias Braun2015-09-091-0/+17
| | | | | | | This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-3/+3
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-9/+5
| | | | llvm-svn: 245895
* MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.Alex Lorenz2015-08-101-1/+4
| | | | | | | | | | | | The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
* LiveInterval: Document and enforce rules about empty subranges.Matthias Braun2015-07-161-0/+2
| | | | | | | | | Empty subranges are not allowed in a LiveInterval and must be removed instead: Check this in the verifiers, put a reminder for this in the comment of the shrinkToUses variant for a single lane and make it automatic for the shrinkToUses variant for a LiveInterval. llvm-svn: 242431
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* MachineFrameInfo: Simplify pristine register calculation.Matthias Braun2015-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | About pristine regsiters: Pristine registers "hold a value that is useless to the current function, but that must be preserved - they are callee saved registers that have not been saved." This concept saves compile time as it frees the prologue/epilogue inserter from adding every such register to every basic blocks live-in list. However the current code in getPristineRegs is formulated in a complicated way: Inside the function prologue and epilogue all callee saves are considered pristine, while in the rest of the code only the non-saved ones are considered pristine. This requires logic to differentiate between prologue/epilogue and the rest and in the presence of shrink-wrapping this even becomes complicated/expensive. It's also unnecessary because the prologue epilogue inserters already mark callee-save registers that are saved/restores properly in the respective blocks in the prologue/epilogue (see updateLiveness() in PrologueEpilogueInserter.cpp). So only declaring non-saved/restored callee saved registers as pristine just works. Differential Revision: http://reviews.llvm.org/D10101 llvm-svn: 238524
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-181-2/+2
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* Fix typoMatt Arsenault2015-04-301-1/+1
| | | | llvm-svn: 236283
* MachineVerifier: Don't crash if MachineOperand has no parentMatt Arsenault2015-04-301-2/+12
| | | | | | | | If you somehow added a MachineOperand to an instruction that did not have the parent set, the verifier would crash since it attempts to use the operand's parent. llvm-svn: 236249
* MachineVerifier: slightly simplify code that is only called with vregsMatthias Braun2015-03-251-30/+25
| | | | llvm-svn: 233216
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-1/+2
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* [llvm] Replacing asserts with static_asserts where appropriateGabor Horvath2015-03-161-1/+1
| | | | | | | | | | | | | | | | Summary: This patch consists of the suggestions of clang-tidy/misc-static-assert check. Reviewers: alexfh Reviewed By: alexfh Subscribers: xazax.hun, llvm-commits Differential Revision: http://reviews.llvm.org/D8343 llvm-svn: 232366
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-1/+1
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Rewrite MachineOperand::print and MachineInstr::print to avoidEric Christopher2015-02-271-1/+1
| | | | | | | | | | | | uses of TM->getSubtargetImpl and propagate to all calls. This could be a debugging regression in places where we had a TargetMachine and/or MachineFunction but don't have it as part of the MachineInstr. Fixing this would require passing a MachineFunction/Function down through the print operator, but none of the existing uses in tree seem to do this. llvm-svn: 230710
* Remove a gross usage of environment variables in MachineVerifier, replacing ↵Owen Anderson2015-02-041-95/+74
| | | | | | | | it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
* MachineVerifier: Allow undef reads if a matching superreg is defined.Matthias Braun2015-01-141-0/+19
| | | | | | | | | | | | | | | | | | | Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 llvm-svn: 226047
* [CodeGen] Let MachineVerifierPass own its banner stringMatthias Braun2014-12-111-5/+5
| | | | llvm-svn: 224041
* LiveInterval: Use range based for loops for subregister ranges.Matthias Braun2014-12-111-7/+6
| | | | llvm-svn: 223991
* LiveInterval: Use more range based for loops for value numbers and segments.Matthias Braun2014-12-101-3/+2
| | | | llvm-svn: 223978
* MachineVerifier: Allow physreg use if just a subreg is defined.Matthias Braun2014-12-101-1/+12
| | | | | | | | We can't mark partially undefined registers, so we have to allow reading a register in the machine verifier if just parts of a register are defined. llvm-svn: 223896
* MachineVerifier: Allow LiveInterval segments to end at a partial write.Matthias Braun2014-12-101-2/+10
| | | | | | | | In the subregister liveness tracking case we do not create implicit reads on partial register writes anymore, still we need to produce a new SSA value for partial writes so the live segment has to end. llvm-svn: 223895
* LiveInterval: Add support to track liveness of subregisters.Matthias Braun2014-12-101-31/+74
| | | | | | This code adds the required data structures. Algorithms to compute it follow. llvm-svn: 223877
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