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* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-111-8/+8
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 312971
* [SystemZ, MachineScheduler] Improve post-RA scheduling.Jonas Paulsson2017-08-171-36/+84
| | | | | | | | | | | | | | | | | | | | | | The idea of this patch is to continue the scheduler state over an MBB boundary in the case where the successor block has only one predecessor. This means that the scheduler will continue in the successor block (after emitting any branch instructions) with e.g. maintained processor resource counters. Benchmarks have been confirmed to benefit from this. The algorithm in MachineScheduler.cpp that extracts scheduling regions of an MBB has been extended so that the strategy may optionally reverse the order of processing the regions themselves. This is controlled by a new method doMBBSchedRegionsTopDown(), which defaults to false. Handling the top-most region of an MBB first also means that a top-down scheduler can continue the scheduler state across any scheduling boundary between to regions inside MBB. Review: Ulrich Weigand, Matthias Braun, Andy Trick. https://reviews.llvm.org/D35053 llvm-svn: 311072
* Mark dump() methods as const. NFCSam Clegg2017-06-211-3/+3
| | | | | | | | | Add const qualifier to any dump() method where adding one was trivial. Differential Revision: https://reviews.llvm.org/D34481 llvm-svn: 305963
* Use range-loop in machine-scheduler. NFCI.Javed Absar2017-06-211-94/+72
| | | | | | | | | | | | Converts to range-loop usage in machine scheduler. This makes the code neater and easier to read, and also keeps pace of the machine scheduler implementation with C++11 features. Reviewed by: Matthias Braun Differential Revision: https://reviews.llvm.org/D34320 llvm-svn: 305887
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* ScheduleDAGInstrs: Fix fixupKills()Matthias Braun2017-05-271-1/+1
| | | | | | | | | | | | Rewrite fixupKills() to use the LivePhysRegs class. Simplifies the code and fixes a bug where the CSR registers in return blocks where missed leading to invalid kill flags. Also remove the unnecessary rule that we wouldn't set kill flags on tied operands. No tests as I have an upcoming commit improving MachineVerifier checks to catch these cases in multiple existing lit tests. llvm-svn: 304055
* CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun2017-05-251-3/+3
| | | | | | | | Rename the DEBUG_TYPE to match the names of corresponding passes where it makes sense. Also establish the pattern of simply referencing DEBUG_TYPE instead of repeating the passname where possible. llvm-svn: 303921
* [AArch64] Make instruction fusion more aggressive. Florian Hahn2017-05-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch makes instruction fusion more aggressive by * adding artificial edges between the successors of FirstSU and SecondSU, similar to BaseMemOpClusterMutation::clusterNeighboringMemOps. * updating PostGenericScheduler::tryCandidate to keep clusters together, similar to GenericScheduler::tryCandidate. This change increases the number of AES instruction pairs generated on Cortex-A57 and Cortex-A72. This doesn't change code at all in most benchmarks or general code, but we've seen improvement on kernels using AESE/AESMC and AESD/AESIMC. Reviewers: evandro, kristof.beyls, t.p.northover, silviu.baranga, atrick, rengolin, MatzeB Reviewed By: evandro Subscribers: aemerson, rengolin, MatzeB, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33230 llvm-svn: 303618
* MachineScheduler: Skip acyclic latency heuristic for in-order coresMatthias Braun2017-04-121-1/+1
| | | | | | | | | | | | | | | | | The current heuristic is triggered on `InFlightCount > BufferLimit` which isn't really helpful on in-order cores where BufferLimit is zero. Note that we already get latency hiding effects for in order cores by instructions staying in the pending queue on stalls; The additional latency scheduling heuristics only have minimal effects after that while occasionally increasing register pressure too much resulting in extra spills. My motivation here is additional spills/reloads ending up in a loop in 464.h264ref / BlockMotionSearch function resulting in a 4% overal regression on an in order core. rdar://30264380 llvm-svn: 300083
* Improve machine schedulers for in-order processorsJaved Absar2017-03-271-0/+28
| | | | | | | | | | | This patch enables schedulers to specify instructions that cannot be issued with any other instructions. It also fixes BeginGroup/EndGroup. Reviewed by: Andrew Trick Differential Revision: https://reviews.llvm.org/D30744 llvm-svn: 298885
* [MachineScheduler] Add missing machine pass dependency.Davide Italiano2017-03-241-0/+1
| | | | llvm-svn: 298736
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-241-2/+2
| | | | | | | | This reverts commit r296009. It broke one out of tree target and also does not account for all partial lines added or removed when calculating PressureDiff. llvm-svn: 296182
* Correct register pressure calculation in presence of subregsStanislav Mekhanoshin2017-02-231-2/+2
| | | | | | | | | | If a subreg is used in an instruction it counts as a whole superreg for the purpose of register pressure calculation. This patch corrects improper register pressure calculation by examining operand's lane mask. Differential Revision: https://reviews.llvm.org/D29835 llvm-svn: 296009
* Fix signed/unsigned comparison warning on MSVCSimon Pilgrim2017-02-231-1/+1
| | | | llvm-svn: 295962
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-221-42/+95
| | | | | | other minor fixes (NFC). llvm-svn: 295893
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-011-74/+0
| | | | | | | | | | | | | This patch moves the class for scheduling adjacent instructions, MacroFusion, to the target. In AArch64, it also expands the fusion to all instructions pairs in a scheduling block, beyond just among the predecessors of the branch at the end. Differential revision: https://reviews.llvm.org/D28489 llvm-svn: 293737
* Cleanup dump() functions.Matthias Braun2017-01-281-5/+9
| | | | | | | | | | | | | | | | | | We had various variants of defining dump() functions in LLVM. Normalize them (this should just consistently implement the things discussed in http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html For reference: - Public headers should just declare the dump() method but not use LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - The definition of a dump method should look like this: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MyClass::dump() { // print stuff to dbgs()... } #endif llvm-svn: 293359
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-161-2/+2
| | | | llvm-svn: 289974
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-3/+3
| | | | | | | | | | | | Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
* MachineScheduler: Export function to construct "default" scheduler.Matthias Braun2016-11-281-20/+12
| | | | | | | | | | | | | | | | | | This makes the createGenericSchedLive() function that constructs the default scheduler available for the public API. This should help when you want to get a scheduler and the default list of DAG mutations. This also shrinks the list of default DAG mutations: {Load|Store}ClusterDAGMutation and MacroFusionDAGMutation are no longer added by default. Targets can easily add them if they need them. It also makes it easier for targets to add alternative/custom macrofusion or clustering mutations while staying with the default createGenericSchedLive(). It also saves the callback back and forth in TargetInstrInfo::enableClusterLoads()/enableClusterStores(). Differential Revision: https://reviews.llvm.org/D26986 llvm-svn: 288057
* Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add ↵Matthias Braun2016-11-111-7/+0
| | | | | | | | | | support to skipping a node." Revert accidentally committed change. This reverts commit r286655. llvm-svn: 286656
* MachineScheduler/ScheduleDAG: Add support to skipping a node.Matthias Braun2016-11-111-0/+7
| | | | | | | | | | | The DAG mutators in the scheduler cannot really remove DAG nodes as additional anlysis information such as ScheduleDAGToplogicalSort are already computed at this point and rely on a fixed number of DAG nodes. Alleviate the missing removal with a new flag: Setting the new skip flag on a node ignores it during scheduling. llvm-svn: 286655
* ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCIMatthias Braun2016-11-111-0/+43
| | | | | | | | | | | | | Push VRegUses/collectVRegUses() down the class hierarchy towards its only user ScheduleDAGMILive. NFCI: The initialization of the map happens at a later point but that should not matter. This is in preparation to allow DAG mutators to merge nodes, which relies on this map getting computed later. llvm-svn: 286654
* MachineScheduler: Dump EntrySU/ExitSU if possibleMatthias Braun2016-11-111-2/+12
| | | | llvm-svn: 286653
* ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()Matthias Braun2016-11-111-30/+20
| | | | | | | | | | | | | | | addSchedBarrierDeps() is supposed to add use operands to the ExitSU node. The current implementation adds uses for calls/barrier instruction and the MBB live-outs in all other cases. The use operands of conditional jump instructions were missed. Also added code to macrofusion to set the latencies between nodes to zero to avoid problems with the fusing nodes lingering around in the pending list now. Differential Revision: https://reviews.llvm.org/D25140 llvm-svn: 286544
* [MachineScheduler] Comments fixing.Jonas Paulsson2016-11-091-1/+2
| | | | | | | | The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed. Review: A Trick llvm-svn: 286350
* Comment rewording in MachineScheduler.cpp.Jonas Paulsson2016-11-041-3/+2
| | | | | Author: A Trick llvm-svn: 285991
* Fix differences in codegen between Linux and Windows toolchainsMandeep Singh Grang2016-10-181-1/+2
| | | | | | | | | | | | | | | | | Summary: There are differences in codegen between Linux and Windows due to: 1. Using std::sort which uses quicksort which is a non-stable sort. 2. Iterating over Set data structure where the iteration order is non deterministic. Reviewers: arsenm, grosbach, junbuml, zinob, MatzeB Subscribers: MatzeB, wdng Differential Revision: https://reviews.llvm.org/D25695 llvm-svn: 284441
* MachineScheduler: Slightly simplify release nodeMatthias Braun2016-09-221-14/+0
| | | | llvm-svn: 282201
* MachineScheduler: Remove ineffective heuristic; NFCMatthias Braun2016-09-221-11/+0
| | | | | | | | | Currently all nodes get added to the NextSU list when they are released, so any candidate must be in that list, making the heuristic ineffective. Remove it for now, we can add it back later in a working fashion if necessary. llvm-svn: 282200
* MachineScheduler: Add constructor functions for the DAGMutationsTom Stellard2016-08-191-4/+40
| | | | | | | | | | | | Summary: This way they can be re-used by target-specific schedulers. Reviewers: atrick, MatzeB, kparzysz Subscribers: kparzysz, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D23678 llvm-svn: 279305
* CodeGen: Avoid dereferencing end() when unconstifying iteratorsDuncan P. N. Exon Smith2016-08-161-8/+4
| | | | | | | | Rather than doing a funny dance that relies on dereferencing end() not crashing, add some API to MachineInstrBundleIterator to get a non-const version of the iterator. llvm-svn: 278870
* CodeGen: Avoid dereferencing end() in MachineSchedulerDuncan P. N. Exon Smith2016-08-111-2/+3
| | | | | | | | | | | | | | | | Check MachineInstr::isDebugValue for the same instruction as we're calling isSchedBoundary, avoiding the possibility of dereferencing end(). This is a functionality change even when I!=end(). Matthias had a look and agrees this is the right resolution (as opposed to checking for end()). This is triggered by a huge number of tests, but they happen to magically pass right now. I found this because WIP patches for PR26753 convert them into crashes. llvm-svn: 278394
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-011-2/+1
| | | | | | | | | | TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* MachineScheduler: Remember top/bottom choice in bidirectional schedulingMatthias Braun2016-06-251-9/+50
| | | | | | | | | | | | | Remember the last choice for the top/bottom scheduling boundary in bidirectional scheduling mode. The top choice should not change if we schedule at the bottom and vice versa. This allows us to improve compiletime: We only recalculate the best pick for one border and re-use the cached top-pick from the other border. Differential Revision: http://reviews.llvm.org/D19350 llvm-svn: 273766
* MachineScheduler: Fully compare top/bottom candidatesMatthias Braun2016-06-251-99/+103
| | | | | | | | | | In bidirectional scheduling this gives more stable results than just comparing the "reason" fields of the top/bottom node because the reason field may be higher depending on what other nodes are in the queue. Differential Revision: http://reviews.llvm.org/D19401 llvm-svn: 273755
* MachineScheduler: Followup to debug message changesMatthias Braun2016-06-231-1/+0
| | | | | | | Do not dump intermediate state of the pending queue anymore now that we always dump the final state before picking. llvm-svn: 273618
* MachineScheduler: Improve debug messagesMatthias Braun2016-06-231-7/+7
| | | | | | | Consistenly display available and pending queues immediately before the scheduling choice is done. llvm-svn: 273615
* CodeGen: Refactor renameDisconnectedComponents() as a passMatthias Braun2016-05-311-10/+2
| | | | | | | | | | | | | | | | | | Refactor LiveIntervals::renameDisconnectedComponents() to be a pass. Also change the name to "RenameIndependentSubregs": - renameDisconnectedComponents() worked on a MachineFunction at a time so it is a natural candidate for a machine function pass. - The algorithm is testable with a .mir test now. - This also fixes a problem where the lazy renaming as part of the MachineScheduler introduced IMPLICIT_DEF instructions after the number of a nodes in a region were counted leading to a mismatch. Differential Revision: http://reviews.llvm.org/D20507 llvm-svn: 271345
* MachineScheduler: Introduce ONLY1 reason to improve debug outputMatthias Braun2016-05-271-6/+13
| | | | llvm-svn: 271058
* LiveIntervalAnalysis: Fix missing defs in renameDisconnectedComponents().Matthias Braun2016-05-201-7/+2
| | | | | | | | | | | | | | Fix renameDisconnectedComponents() creating vreg uses that can be reached from function begin withouthaving a definition (or explicit live-in). Fix this by inserting IMPLICIT_DEF instruction before control-flow joins as necessary. Removes an assert from MachineScheduler because we may now get additional IMPLICIT_DEF when preparing the scheduling policy. This fixes the underlying problem of http://llvm.org/PR27705 llvm-svn: 270259
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-5/+11
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* Re-commit optimization bisect support (r267022) without new pass manager ↵Andrew Kaylor2016-04-221-2/+2
| | | | | | | | | | support. The original commit was reverted because of a buildbot problem with LazyCallGraph::SCC handling (not related to the OptBisect handling). Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267231
* MachineScheduler: Move code to initialize a Candidate out of tryCandidate(); NFCMatthias Braun2016-04-221-33/+33
| | | | llvm-svn: 267191
* MachineScheduler: Limit the size of the ready list.Matthias Braun2016-04-221-1/+10
| | | | | | | | | Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. Differential Revision: http://reviews.llvm.org/D19349 llvm-svn: 267189
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-221-2/+2
| | | | | | | | This reverts commit r267022, due to an ASan failure: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549 llvm-svn: 267115
* Initial implementation of optimization bisect support.Andrew Kaylor2016-04-211-2/+2
| | | | | | | | | | | | This patch implements a optimization bisect feature, which will allow optimizations to be selectively disabled at compile time in order to track down test failures that are caused by incorrect optimizations. The bisection is enabled using a new command line option (-opt-bisect-limit). Individual passes that may be skipped call the OptBisect object (via an LLVMContext) to see if they should be skipped based on the bisect limit. A finer level of control (disabling individual transformations) can be managed through an addition OptBisect method, but this is not yet used. The skip checking in this implementation is based on (and replaces) the skipOptnoneFunction check. Where that check was being called, a new call has been inserted in its place which checks the bisect limit and the optnone attribute. A new function call has been added for module and SCC passes that behaves in a similar way. Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267022
* MachineSched: Cleanup; NFCMatthias Braun2016-04-211-32/+16
| | | | llvm-svn: 266946
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