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authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-02-23 20:19:44 +0000
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-02-23 20:19:44 +0000
commitce3ddd2de4c5dbd5a7a68b51ea38f96cf7fbf3aa (patch)
tree05d2e6754a3580a96a723b01dcd89dcf58eec2bb /llvm/lib/CodeGen/MachineScheduler.cpp
parent851125dca903fdaa458d87fb0a35349286a2395f (diff)
downloadbcm5719-llvm-ce3ddd2de4c5dbd5a7a68b51ea38f96cf7fbf3aa.tar.gz
bcm5719-llvm-ce3ddd2de4c5dbd5a7a68b51ea38f96cf7fbf3aa.zip
Correct register pressure calculation in presence of subregs
If a subreg is used in an instruction it counts as a whole superreg for the purpose of register pressure calculation. This patch corrects improper register pressure calculation by examining operand's lane mask. Differential Revision: https://reviews.llvm.org/D29835 llvm-svn: 296009
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 79b02c7de8c..066398358e8 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1085,7 +1085,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
continue;
PressureDiff &PDiff = getPressureDiff(&SU);
- PDiff.addPressureChange(Reg, Decrement, &MRI);
+ PDiff.addPressureChange(P, Decrement, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
<< PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
@@ -1123,7 +1123,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
- PDiff.addPressureChange(Reg, true, &MRI);
+ PDiff.addPressureChange(P, true, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
<< *SU->getInstr();
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