summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineLICM.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* MachineLICM: Use TargetSchedModel instead of just itinerariesMatthias Braun2015-06-131-11/+10
| | | | | | | | | This will use Itinieraries if available, but will also work if just a MCSchedModel is available. Differential Revision: http://reviews.llvm.org/D10428 llvm-svn: 239658
* CodeGen: Use mop_iterator instead of MIOperands/ConstMIOperandsMatthias Braun2015-05-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | MIOperands/ConstMIOperands are classes iterating over the MachineOperand of a MachineInstr, however MachineInstr::mop_iterator does the same thing. I assume these two iterators exist to have a uniform interface to iterate over the operands of a machine instruction bundle and a single machine instruction. However in practice I find it more confusing to have 2 different iterator classes, so this patch transforms (nearly all) the code to use mop_iterators. The only exception being MIOperands::anlayzePhysReg() and MIOperands::analyzeVirtReg() still needing an equivalent, I leave that as an exercise for the next patch. Differential Revision: http://reviews.llvm.org/D9932 This version is slightly modified from the proposed revision in that it introduces MachineInstr::getOperandNo to avoid the extra counting variable in the few loops that previously used MIOperands::getOperandNo. llvm-svn: 238539
* MachineInstr: Remove unused parameter.Matthias Braun2015-05-191-1/+1
| | | | llvm-svn: 237726
* [MachineLICM] Use newer model of register pressure sets.Daniel Jasper2015-04-141-43/+32
| | | | | | | | | | | | | | | | TargetRegisterInfo::getRegPressureLimit has a note that it is an old model that relies on manually entered classes. Using the newer model of register pressure sets seems more appropriate. We might eventually even switch to lib/CodeGen/RegisterPressure.cpp, but we should probably do incremental changes here. Using the newer model also makes it easier to take regmasks into account which is necessary to fix llvm.org/PR23143. I am currently also preparing a patch for that, but would like to do this switch independently. Review: http://reviews.llvm.org/D8986 llvm-svn: 234880
* [MachineLICM] Cleanup, remove unused parameters. NFC.Daniel Jasper2015-04-081-13/+7
| | | | llvm-svn: 234392
* Cleanup register pressure calculation in MachineLICM.Daniel Jasper2015-04-071-107/+65
| | | | | | | | | | | | | | | There were four almost identical implementations of calculating/updating the register pressure for a certain MachineInstr. Cleanup to have a single implementation (well, controlled with two bool flags until this is cleaned up more). No functional changes intended. Tested by verify that there are no binary changes in the entire llvm test-suite. A new test was added separately in r234309 as it revealed a pre-existing error in the register pressure calculation. llvm-svn: 234325
* [MachineLICM] Remove obsolete comment about not considering reg pressure.Daniel Jasper2015-04-071-4/+0
| | | | llvm-svn: 234310
* [MachineLICM] Small cleanup: Constify and rangeify.Daniel Jasper2015-04-031-12/+9
| | | | | | NFC. llvm-svn: 234018
* [MachineLICM] First steps of sinking GEPs near calls.Daniel Jasper2015-03-141-0/+61
| | | | | | | | | | | | | | | Specifically, if there are copy-like instructions in the loop header they are moved into the loop close to their uses. This reduces the live intervals of the values and can avoid register spills. This is working towards a fix for http://llvm.org/PR22230. Review: http://reviews.llvm.org/D7259 Next steps: - Find a better cost model (which non-copy instructions should be sunk?) - Make this dependent on register pressure llvm-svn: 232262
* Small cleanup of MachineLICM.cppDaniel Jasper2015-02-051-15/+12
| | | | | | | | | | | | | Specifically: - Calculate the loop pre-header once at the stat of HoistOutOfLoop, so: - We don't-DFS walk the MachineDomTree if we aren't going to do anything - Don't call getCurPreheader for each Scope - Don't needlessly use a do-while loop - Use early exit for Scopes.size() == 0 No functional changes intended. llvm-svn: 228350
* [MachineLICM] A command-line option to hoist even cheap instructionsHal Finkel2015-01-081-1/+6
| | | | | | | | Add a command-line option to enable hoisting even cheap instructions (in low-register-pressure situations). This is turned off by default, but has proved useful for testing purposes. llvm-svn: 225470
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-191-2/+2
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* Remove the use and member variable of the TargetMachine fromEric Christopher2014-10-141-6/+4
| | | | | | MachineLICM as we can get the same data off of the MachineFunction. llvm-svn: 219663
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-031-17/+3
| | | | llvm-svn: 218999
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+5
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Add TargetInstrInfo interface isAsCheapAsAMove.Jiangning Liu2014-07-291-1/+1
| | | | llvm-svn: 214158
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-151-6/+5
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-14/+14
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-311-0/+3
| | | | | | | pass normally runs at optimization level None, or is part of the register allocation pipeline. llvm-svn: 205228
* Switch a number of loops in lib/CodeGen over to range-based for-loops, now thatOwen Anderson2014-03-171-18/+12
| | | | | | the MachineRegisterInfo iterators are compatible with it. llvm-svn: 204075
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-4/+6
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-3/+3
| | | | | | class. llvm-svn: 203220
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-2/+2
| | | | llvm-svn: 190770
* Fix overly pessimistic shortcut in post-RA MachineLICMRichard Sandiford2013-08-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers and TermRegs. When it sees a definition of R it adds all aliases of R to the corresponding set, so that when it needs to test for membership it only needs to test a single register, rather than worrying about aliases there too. E.g. the final candidate loop just has: unsigned Def = Candidates[i].Def; if (!PhysRegClobbers.test(Def) && ...) { to test whether register Def is multiply defined. However, there was also a shortcut in ProcessMI to make sure we didn't add candidates if we already knew that they would fail the final test. This shortcut was more pessimistic than the final one because it checked whether _any alias_ of the defined register was multiply defined. This is too conservative for targets that define register pairs. E.g. on z, R0 and R1 are sometimes used as a pair, so there is a 128-bit register that aliases both R0 and R1. If a loop used R0 and R1 independently, and the definition of R0 came first, we would be able to hoist the R0 assignment (because that used the final test quoted above) but not the R1 assignment (because that meant we had two definitions of the paired R0/R1 register and would fail the shortcut in ProcessMI). This patch just uses the same check for the ProcessMI shortcut as we use in the final candidate loop. llvm-svn: 188774
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-111-4/+4
| | | | | | size. llvm-svn: 186098
* Split TargetLowering into a CodeGen and a SelectionDAG part.Benjamin Kramer2013-01-111-1/+1
| | | | | | | | | This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. llvm-svn: 172246
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-1/+1
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169854
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-1/+1
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-8/+8
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-7/+7
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Tweak MachineLICM heuristics for cheap instructions.Jakob Stoklund Olesen2012-04-111-69/+89
| | | | | | | | | | | Allow cheap instructions to be hoisted if they are register pressure neutral or better. This happens if the instruction is the last loop use of another virtual register. Only expensive instructions are allowed to increase loop register pressure. llvm-svn: 154455
* Only check for PHI uses inside the current loop.Jakob Stoklund Olesen2012-04-111-27/+51
| | | | | | | | | | | Hoisting a value that is used by a PHI in the loop will introduce a copy because the live range is extended to cross the PHI. The same applies to PHIs in exit blocks. Also use this opportunity to make HasLoopPHIUse() non-recursive. llvm-svn: 154454
* Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng2012-03-271-4/+28
| | | | | | | | register that's read by the preheader terminator. rdar://11095580 llvm-svn: 153492
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-3/+3
| | | | llvm-svn: 152001
* Fix 80-column violation.Chad Rosier2012-02-281-2/+2
| | | | llvm-svn: 151599
* Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."Jakob Stoklund Olesen2012-02-171-11/+0
| | | | | | | | | | This caused miscompilations on out-of-tree targets, and possibly i386 as well. I'll find some other way of hoisting %rip-relative loads from loops containing calls. llvm-svn: 150816
* Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen2012-02-111-0/+11
| | | | | | | | When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. llvm-svn: 150288
* Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen2012-02-111-6/+6
| | | | llvm-svn: 150286
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-6/+1
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: MachineLICM.Andrew Trick2012-02-081-4/+5
| | | | llvm-svn: 150099
* whitespaceAndrew Trick2012-02-081-11/+11
| | | | llvm-svn: 150098
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-4/+1
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-4/+4
| | | | | | This fixes a typo in r148589. llvm-svn: 148724
* Simplify debug output.Jakob Stoklund Olesen2012-01-231-10/+2
| | | | llvm-svn: 148723
* Support register masks in MachineLICM.Jakob Stoklund Olesen2012-01-201-23/+36
| | | | | | Only PostRA LICM is affected. llvm-svn: 148589
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-161-14/+1
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
OpenPOWER on IntegriCloud