summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineLICM.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-151-6/+5
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-14/+14
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson2014-03-311-0/+3
| | | | | | | pass normally runs at optimization level None, or is part of the register allocation pipeline. llvm-svn: 205228
* Switch a number of loops in lib/CodeGen over to range-based for-loops, now thatOwen Anderson2014-03-171-18/+12
| | | | | | the MachineRegisterInfo iterators are compatible with it. llvm-svn: 204075
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-4/+6
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-071-3/+3
| | | | | | class. llvm-svn: 203220
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-2/+2
| | | | llvm-svn: 190770
* Fix overly pessimistic shortcut in post-RA MachineLICMRichard Sandiford2013-08-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers and TermRegs. When it sees a definition of R it adds all aliases of R to the corresponding set, so that when it needs to test for membership it only needs to test a single register, rather than worrying about aliases there too. E.g. the final candidate loop just has: unsigned Def = Candidates[i].Def; if (!PhysRegClobbers.test(Def) && ...) { to test whether register Def is multiply defined. However, there was also a shortcut in ProcessMI to make sure we didn't add candidates if we already knew that they would fail the final test. This shortcut was more pessimistic than the final one because it checked whether _any alias_ of the defined register was multiply defined. This is too conservative for targets that define register pairs. E.g. on z, R0 and R1 are sometimes used as a pair, so there is a 128-bit register that aliases both R0 and R1. If a loop used R0 and R1 independently, and the definition of R0 came first, we would be able to hoist the R0 assignment (because that used the final test quoted above) but not the R1 assignment (because that meant we had two definitions of the paired R0/R1 register and would fail the shortcut in ProcessMI). This patch just uses the same check for the ProcessMI shortcut as we use in the final candidate loop. llvm-svn: 188774
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-111-4/+4
| | | | | | size. llvm-svn: 186098
* Split TargetLowering into a CodeGen and a SelectionDAG part.Benjamin Kramer2013-01-111-1/+1
| | | | | | | | | This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still a complete mess but as long as the edges consist of virtual call it doesn't cause breakage. BasicTTI did static calls and thus broke some build configurations. llvm-svn: 172246
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-1/+1
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169854
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-1/+1
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-8/+8
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-7/+7
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Tweak MachineLICM heuristics for cheap instructions.Jakob Stoklund Olesen2012-04-111-69/+89
| | | | | | | | | | | Allow cheap instructions to be hoisted if they are register pressure neutral or better. This happens if the instruction is the last loop use of another virtual register. Only expensive instructions are allowed to increase loop register pressure. llvm-svn: 154455
* Only check for PHI uses inside the current loop.Jakob Stoklund Olesen2012-04-111-27/+51
| | | | | | | | | | | Hoisting a value that is used by a PHI in the loop will introduce a copy because the live range is extended to cross the PHI. The same applies to PHIs in exit blocks. Also use this opportunity to make HasLoopPHIUse() non-recursive. llvm-svn: 154454
* Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng2012-03-271-4/+28
| | | | | | | | register that's read by the preheader terminator. rdar://11095580 llvm-svn: 153492
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-3/+3
| | | | llvm-svn: 152001
* Fix 80-column violation.Chad Rosier2012-02-281-2/+2
| | | | llvm-svn: 151599
* Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."Jakob Stoklund Olesen2012-02-171-11/+0
| | | | | | | | | | This caused miscompilations on out-of-tree targets, and possibly i386 as well. I'll find some other way of hoisting %rip-relative loads from loops containing calls. llvm-svn: 150816
* Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen2012-02-111-0/+11
| | | | | | | | When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. llvm-svn: 150288
* Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen2012-02-111-6/+6
| | | | llvm-svn: 150286
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-6/+1
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* Move pass configuration out of pass constructors: MachineLICM.Andrew Trick2012-02-081-4/+5
| | | | llvm-svn: 150099
* whitespaceAndrew Trick2012-02-081-11/+11
| | | | llvm-svn: 150098
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-4/+1
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-4/+4
| | | | | | This fixes a typo in r148589. llvm-svn: 148724
* Simplify debug output.Jakob Stoklund Olesen2012-01-231-10/+2
| | | | llvm-svn: 148723
* Support register masks in MachineLICM.Jakob Stoklund Olesen2012-01-201-23/+36
| | | | | | Only PostRA LICM is affected. llvm-svn: 148589
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-161-14/+1
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
* 80 col violation.Evan Cheng2012-01-101-2/+2
| | | | llvm-svn: 147884
* Hoisted some loop invariant smallvector lookups out of a MachineLICM loopPete Cooper2011-12-221-1/+3
| | | | llvm-svn: 147127
* Changed MachineLICM to use a worklist list MachineCSE instead of recursion.Pete Cooper2011-12-221-44/+125
| | | | | | Fixes <rdar://problem/10584116> llvm-svn: 147125
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-2/+3
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-1/+1
| | | | llvm-svn: 144747
* Disable LICM speculation in high register pressure situation again now that ↵Evan Cheng2011-10-261-1/+1
| | | | | | Devang has fixed other issues. llvm-svn: 143003
* As Evan suggested, loads from constant pool are safe to speculate.Devang Patel2011-10-201-5/+5
| | | | llvm-svn: 142593
* Add a comment.Devang Patel2011-10-201-1/+3
| | | | llvm-svn: 142592
* Constraint register class with constrainRegClass() to CSE a virtual into ↵Evan Cheng2011-10-171-3/+26
| | | | | | another. rdar://10293289 llvm-svn: 142234
* It is safe to speculate load from GOT. This fixes performance regression ↵Devang Patel2011-10-171-1/+17
| | | | | | | | caused by r141689. Radar 10281206. llvm-svn: 142202
* Tabs to spaces.Nick Lewycky2011-10-131-2/+2
| | | | llvm-svn: 141844
* Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng2011-10-121-6/+15
| | | | | | to investigate the regressions. llvm-svn: 141813
* Expand the check for a landing pad so that it looks at the basic block'sBill Wendling2011-10-121-5/+11
| | | | | | | containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. llvm-svn: 141767
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* N.B. This is with the new EH scheme:Bill Wendling2011-10-111-0/+5
| | | | | | | | | | | | | | | The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. llvm-svn: 141726
OpenPOWER on IntegriCloud