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path: root/llvm/lib/CodeGen/MachineLICM.cpp
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* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng2011-04-111-8/+17
| | | | | | more copies. rdar://9266679 llvm-svn: 129297
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-1/+1
| | | | llvm-svn: 127175
* Sorry, several patches in one.Evan Cheng2011-01-201-40/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-4/+4
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Add a FIXME comment.Dan Gohman2010-11-111-0/+2
| | | | llvm-svn: 118803
* MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen2010-11-011-1/+0
| | | | | | edges on demand. llvm-svn: 117982
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-4/+36
| | | | llvm-svn: 117348
* More accurate estimate / tracking of register pressure.Evan Cheng2010-10-201-64/+121
| | | | | | | | | | - Initial register pressure in the loop should be all the live defs into the loop. Not just those from loop preheader which is often empty. - When an instruction is hoisted, update register pressure from loop preheader to the original BB. - Treat only use of a virtual register as kill since the code is still SSA. llvm-svn: 116956
* Make CodeGen TBAA-aware.Dan Gohman2010-10-201-1/+3
| | | | llvm-svn: 116890
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-191-77/+58
| | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-2/+6
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-191-36/+52
| | | | | | is", which breaks some nightly tests. llvm-svn: 116816
* Fix for machine licm assert: RCCost <= RegPressure[RCId]Andrew Trick2010-10-191-2/+2
| | | | | | | in MultiSource/Benchmarks/VersaBench/beamformer/beamformer. SmallSet.insert returns true if the element is inserted. llvm-svn: 116790
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-191-52/+36
| | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781
* More machine LICM work. It now tracks register pressure for path from ↵Evan Cheng2010-10-161-69/+155
| | | | | | preheader to current BB and use the information determine whether hoisting is worthwhile. llvm-svn: 116654
* Register pressure and instruction latency aware machine LICM. Work in progress.Evan Cheng2010-10-141-26/+242
| | | | llvm-svn: 116465
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+6
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Don't waste time unfolding simple loads. The unfolded copy won't be hoisted.Evan Cheng2010-10-081-0/+4
| | | | llvm-svn: 116081
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Comment typo.Dale Johannesen2010-07-291-1/+1
| | | | llvm-svn: 109765
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+2
| | | | llvm-svn: 109045
* Fix test for switch statements and increaseDale Johannesen2010-07-201-2/+3
| | | | | | threshold a bit per experimentation. llvm-svn: 108935
* Don't hoist things out of a large switch inside aDale Johannesen2010-07-201-2/+6
| | | | | | | | | | loop, for the reasons in the comments. This is a major win on 253.perlbmk on ARM Darwin. I expect it to be a good heuristic in general, but it's possible some things will regress; I'll be watching. 7940152. llvm-svn: 108792
* Teach ProcessImplicitDefs to transform more COPY instructions into ↵Evan Cheng2010-07-141-6/+3
| | | | | | IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. llvm-svn: 108304
* change machinelicm to use MachineInstr::isSafeToMove. NoChris Lattner2010-07-121-18/+8
| | | | | | | | intended functionality change. The avoidance of hoistiing implicitdef seems wrong though. llvm-svn: 108109
* Fix MachineLICM to actually visit inner loops.Dan Gohman2010-07-091-3/+11
| | | | llvm-svn: 108001
* Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman2010-06-221-23/+50
| | | | | | | into a utility routine, teach it how to update MachineLoopInfo, and make use of it in MachineLICM to split critical edges on demand. llvm-svn: 106555
* Doh. Machine LICM is re-initializing the CSE map over and over. Patch by ↵Evan Cheng2010-05-291-2/+7
| | | | | | Anna Zaks. rdar://8037934. llvm-svn: 105065
* Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman2010-05-131-1/+12
| | | | | | when they move instructions. llvm-svn: 103737
* When MachineLICM is hoisting a physical register after regalloc, make sure theJakob Stoklund Olesen2010-04-201-4/+17
| | | | | | | | | | | register is not killed in the loop. This fixes 188.ammp on ARM where the post-ra scheduler would grab a register that looked available but wasn't. A testcase would be huge and fragile, sorry. llvm-svn: 101930
* Postra machine licm must add registers defined by loop invariants to *all* ofEvan Cheng2010-04-171-48/+23
| | | | | | | | the live-in sets of BBs in the loop. Otherwise later pass may end up using the registers and override the invariant. rdar://7852937 No reasonablly sized test case possible. llvm-svn: 101626
* Fast path implicit_def check.Evan Cheng2010-04-131-5/+5
| | | | llvm-svn: 101183
* Avoid variable shadowing.Evan Cheng2010-04-131-2/+2
| | | | llvm-svn: 101170
* Expand postra machine licm's capability a little more. If an instruction's ↵Evan Cheng2010-04-131-8/+24
| | | | | | register operands are all loop invariants, then it's safe to hoist it. llvm-svn: 101167
* Teach postra machine licm to hoist more obvious invariants, e.g. ↵Evan Cheng2010-04-131-17/+38
| | | | | | instructions with no source operands. llvm-svn: 101154
* Eliminate MachineBasicBlock::const_livein_iterator and makeDan Gohman2010-04-131-1/+1
| | | | | | | | MachineBasicBlock::livein_iterator a const_iterator, because clients shouldn't ever be using the iterator interface to mutate the livein set. llvm-svn: 101147
* Plug trivial leak.Benjamin Kramer2010-04-121-0/+2
| | | | llvm-svn: 101034
* Delete this obsolete comment.Dan Gohman2010-04-091-4/+0
| | | | llvm-svn: 100858
* Make post regalloc machine licm functional. It now passes all of MultiSource.Evan Cheng2010-04-081-79/+169
| | | | llvm-svn: 100742
* Add comments for missed opportunities.Evan Cheng2010-04-071-1/+4
| | | | llvm-svn: 100610
* Fix typo.Evan Cheng2010-04-071-1/+1
| | | | llvm-svn: 100609
* Post regalloc LICM. Work in progress.Evan Cheng2010-04-071-11/+162
| | | | llvm-svn: 100592
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-031-1/+1
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Don't try to replace physical registers when doing CSE.Dan Gohman2010-02-281-1/+12
| | | | llvm-svn: 97360
* Don't unconditionally suppress hoisting of instructions with implicitDan Gohman2010-02-281-26/+4
| | | | | | | | defs or uses. The regular def and use checking below covers them, and can be more precise. It's safe to hoist an instruction with a dead implicit def if the register isn't live into the loop header. llvm-svn: 97352
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