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path: root/llvm/lib/CodeGen/MachineCSE.cpp
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* MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps ↵Benjamin Kramer2012-08-111-4/+3
| | | | | | already. llvm-svn: 161729
* PR13578: Teach MachineCSE that instructions that use a constant register can ↵Benjamin Kramer2012-08-111-2/+5
| | | | | | | | be CSE'd safely. This is common e.g. when doing rip-relative addressing on x86_64. llvm-svn: 161728
* X86: enable CSE between CMP and SUBManman Ren2012-08-081-2/+18
| | | | | | | | | | | | | | We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 llvm-svn: 161462
* MachineCSE: Update the heuristics for isProfitableToCSE.Manman Ren2012-08-071-0/+23
| | | | | | | | | If the result of a common subexpression is used at all uses of the candidate expression, CSE should not increase the live range of the common subexpression. rdar://11393714 and rdar://11819721 llvm-svn: 161396
* Remove tabs.Bill Wendling2012-07-191-1/+1
| | | | llvm-svn: 160475
* Remove ParentMap. You can just ask the domnode for its parent. No functionalityNick Lewycky2012-07-051-11/+8
| | | | | | | | | | change. Move the "Not profitable, avoid CSE!" debug message next to where we fail the check for profitability and use a different message for avoiding CSE due to being in different register classes. llvm-svn: 159729
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-3/+2
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Handle regmasks in MachineCSE.Jakob Stoklund Olesen2012-02-281-0/+6
| | | | | | | | Don't attempt to extend physreg live ranges across calls. <rdar://problem/10942095> llvm-svn: 151610
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames2012-02-171-3/+9
| | | | | | bail on reserved registers. This *should* be safe as of r150786. llvm-svn: 150769
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-9/+3
| | | | llvm-svn: 150655
* MachineCSE shouldn't extend the live ranges of reserved or allocatable ↵Lang Hames2012-02-161-3/+9
| | | | | | registers. llvm-svn: 150653
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-2/+1
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* whitespaceAndrew Trick2012-02-081-2/+2
| | | | llvm-svn: 150094
* Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands2012-02-051-0/+1
| | | | llvm-svn: 149834
* Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng2012-01-111-4/+12
| | | | | | the physical registers are not allocatable. llvm-svn: 147902
* Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng2012-01-101-15/+54
| | | | | | | | | | define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 llvm-svn: 147827
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-5/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* We need to verify that the machine instruction we're using as a replacement forBill Wendling2011-10-121-0/+11
| | | | | | | | | | our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Re-revert r130877; it's apparently causing a regression on 197.parser,Eli Friedman2011-05-061-50/+27
| | | | | | possibly related to cbnz formation. llvm-svn: 130977
* Minor correction to r130877; fixes PR9846 and hopefully the buildbot failures.Eli Friedman2011-05-051-1/+2
| | | | llvm-svn: 130925
* Re-commit r130862 with a minor change to avoid an iterator running off the ↵Eli Friedman2011-05-041-27/+49
| | | | | | | | | | edge in some cases. Original message: Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130877
* Back out r130862; it appears to be breaking bootstrap.Eli Friedman2011-05-041-43/+27
| | | | llvm-svn: 130867
* Teach MachineCSE how to do simple cross-block CSE involving physregs. This ↵Eli Friedman2011-05-041-27/+43
| | | | | | allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130862
* Fix a couple of places where changes are made but not tracked.Evan Cheng2011-04-111-2/+6
| | | | llvm-svn: 129287
* fit in 80 cols and use MBB::isSuccessor instead of a handChris Lattner2011-01-101-5/+4
| | | | | | rolled std::find. llvm-svn: 123164
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-2/+2
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Use a RecyclingAllocator to allocate values for MachineCSE's ScopedHashTable forCameron Zwarich2011-01-031-3/+7
| | | | | | a 28% speedup of MachineCSE time on 403.gcc. llvm-svn: 122735
* Teach machine cse to commute instructions.Evan Cheng2010-12-151-2/+19
| | | | llvm-svn: 121903
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-1/+3
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+5
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-061-7/+2
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. llvm-svn: 115875
* Machine CSE was forgetting to clear some data structures.Evan Cheng2010-09-171-0/+7
| | | | llvm-svn: 114222
* Fix a potential bug that can cause miscomparison with and without debug info.Evan Cheng2010-09-171-1/+1
| | | | llvm-svn: 114220
* Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after ↵Evan Cheng2010-08-171-0/+1
| | | | | | machine cse before. llvm-svn: 111281
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-211-2/+2
| | | | llvm-svn: 109045
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-30/+4
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-0/+22
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Detect and handle COPY in many places.Jakob Stoklund Olesen2010-07-031-2/+2
| | | | | | | This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. llvm-svn: 107547
* Re-apply 105308 with fix.Evan Cheng2010-06-041-7/+13
| | | | llvm-svn: 105502
* Revert 105308.Bob Wilson2010-06-031-1/+4
| | | | llvm-svn: 105399
* Enable machine cse of instructions which define physical registers.Evan Cheng2010-06-021-4/+1
| | | | llvm-svn: 105308
* Make this LookAheadLimit, not the uninitialized LookAheadLeft.Eric Christopher2010-05-211-1/+1
| | | | | | Evan please verify! llvm-svn: 104408
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