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* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-111-43/+65
| | | | | | | | | | | | | | | | | | | | | | This changes MachineRegisterInfo to be initializes after parsing all instructions. This is in preparation for upcoming commits that allow the register class specification on the operand or deduce them from the MCInstrDesc. This commit removes the unused feature of having nonsequential register numbers. This was confusing anyway as the vreg numbers would be different after parsing when you had "holes" in your numbering. This patch also introduces the concept of an incomplete virtual register. An incomplete virtual register may be used during .mir parsing to construct MachineOperands without knowing the exact register class (or register bank) yet. NFC except for some error messages. Differential Revision: https://reviews.llvm.org/D22397 llvm-svn: 283848
* [MIRParser] Delete dead code. NFCI.Davide Italiano2016-09-211-12/+0
| | | | llvm-svn: 282098
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-171-3/+3
| | | | | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. This is a recommit of r281806 after fixing the accessor to return a pointer instead of a reference and updating all the call-sites. llvm-svn: 281813
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-5/+1
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-151-1/+3
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-121-6/+21
| | | | | | | | | | | | | | | | | Some generic instructions have multiple types. While in theory these always be discovered by inspecting the single definition of each generic vreg, in practice those definitions won't always be local and traipsing through a big function to find them will not be fun. So this changes MIRPrinter to print out the type of uses as well as defs, if they're known to be different or not known to be the same. On the parsing side, we're a little more flexible: provided each register is given a type in at least one place it's mentioned (and all types are consistent) we accept the MIR. This doesn't introduce ambiguity but makes writing tests manually a bit less painful. llvm-svn: 281204
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-0/+3
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-26/+6
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* [MC] Move .cv_loc management logic out of MCContextReid Kleckner2016-08-261-0/+1
| | | | | | | | | | | MCContext already has many tasks, and separating CodeView out from it is probably a good idea. The .cv_loc tracking was modelled on the DWARF tracking which lived directly in MCContext. Removes the inclusion of MCCodeView.h from MCContext.h, so now there are only 10 build actions while I hack on CodeView support instead of 265. llvm-svn: 279847
* GlobalISel: legalize integer comparisons on AArch64.Tim Northover2016-08-231-1/+1
| | | | | | | Next step is doing both legalizations at the same time! Marvel at GlobalISel's cunning. llvm-svn: 279566
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+62
| | | | llvm-svn: 278969
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-1/+1
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-291-0/+34
| | | | | | | This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-1/+1
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [MIRParser] Accept unsized generic instructions.Ahmed Bougacha2016-07-281-6/+2
| | | | | | | Since r276158, we require generic instructions to have a sized type. G_BR doesn't; relax the restriction. llvm-svn: 277006
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-261-3/+3
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-261-4/+10
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* GlobalISel: allow multiple types on MachineInstrs.Tim Northover2016-07-221-7/+14
| | | | llvm-svn: 276481
* GlobalISel: implement alloca instructionTim Northover2016-07-221-2/+8
| | | | llvm-svn: 276433
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-35/+42
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-191-1/+5
| | | | | | | | | | Also verify that we never try to set the size of a vreg associated to a register class. Report an error when we encounter that in MIR. Fix a testcase that hit that error and had a size for no reason. llvm-svn: 276012
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+2
| | | | llvm-svn: 275658
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-151-4/+4
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFCMatthias Braun2016-07-131-52/+29
| | | | | | | | Code cleanup: Move references to SlotMapping and SourceMgr into the PerFunctionMIParsingState to avoid unnecessary passing around in parameters. llvm-svn: 275342
* MIRParser: Move MachineFunction reference into PFS; NFCMatthias Braun2016-07-131-33/+34
| | | | | | | | | | Code cleanup: The PerFunctionMIParsingState is per function, moving a reference into PFS we can avoid passing around the MachineFunction in an extra parameter most of the time. Also change most signatures to consistently pass PFS reference first. llvm-svn: 275329
* [MIR] Check that generic virtual registers get a size.Quentin Colombet2016-06-081-4/+6
| | | | | | | | Without that check it was possible to write test cases where the size was not specified and we ended up with weird asserts down the road, because the default value (1) would not make sense. llvm-svn: 272226
* MIR: Fix parsing of stack object references in MachineMemOperandsMatthias Braun2016-06-081-1/+10
| | | | | | | The MachineMemOperand parser lacked the code to handle %stack.X references (%fixed-stack.X was working). llvm-svn: 272082
* MIR: Support MachineMemOperands without associated valueMatthias Braun2016-06-041-7/+9
| | | | | | | This is allowed (though used rarely) and useful to keep your tests short. llvm-svn: 271752
* MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun2016-03-281-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D18279 llvm-svn: 264608
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-081-14/+29
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-081-0/+33
| | | | llvm-svn: 262879
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-071-8/+36
| | | | llvm-svn: 262862
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-2/+2
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-011-2/+1
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* Fix PR 24724 - The implicit register verifier shouldn't assume certain operandAlex Lorenz2015-09-101-39/+16
| | | | | | | | | | order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. llvm-svn: 247283
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-1/+1
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-211-2/+11
| | | | | | memory operands. llvm-svn: 245745
* MIRParser: Split the 'parseIRConstant' method into two methods. NFC.Alex Lorenz2015-08-211-3/+12
| | | | | | | One variant of this method can be reused when parsing the quoted IR pointer expressions in the machine memory operands. llvm-svn: 245743
* MIR Serialization: Print MCSymbol operands.Alex Lorenz2015-08-211-1/+1
| | | | | | | | This commit allows the MIR printer to print the MCSymbol machine operands. Unfortunately they can't be parsed at this time. I will create a bug that will track the fact that the MCSymbol operands can't be parsed yet. llvm-svn: 245737
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-201-4/+11
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-201-13/+20
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-191-4/+45
| | | | llvm-svn: 245521
* MIR Parser: parseIRValue should take in a constant pointer. NFC.Alex Lorenz2015-08-191-3/+3
| | | | llvm-svn: 245520
* MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.Alex Lorenz2015-08-191-14/+13
| | | | | | | Besides storing the operand's source range, this structure now stores other attributes as well, so the name should reflect this fact. llvm-svn: 245483
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-191-14/+93
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-191-0/+4
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-191-0/+18
| | | | llvm-svn: 245396
* MIR Parser: Return true on error when parsing standalone registers.Alex Lorenz2015-08-181-2/+2
| | | | llvm-svn: 245384
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