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path: root/llvm/lib/CodeGen/MIRParser/MIParser.cpp
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* CodeGen: Cleanup regmask construction; NFCMatthias Braun2018-07-261-6/+2
* [CodeGen] Fix inconsistent declaration parameter nameFangrui Song2018-07-161-2/+2
* [MIRParser] Update a diagnostic message to use the correct register sigil. NFCMatt Davis2018-06-191-1/+1
* [MIRParser] Add parser support for 'true' and 'false' i1s.Amara Emerson2018-06-051-2/+5
* [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin2018-05-081-13/+20
* [MIRPraser] Improve error checking for typed immediate operandsHeejin Ahn2018-05-051-6/+13
* [MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn2018-05-051-7/+18
* MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg2018-05-031-6/+29
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-0/+26
* [MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih2018-03-131-5/+7
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-261-0/+16
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-091-0/+3
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-11/+11
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-151-0/+67
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-131-1/+0
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-1/+6
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-0/+2
* [mir] Print/Parse both MOLoad and MOStore when they occur together.Daniel Sanders2017-11-281-1/+11
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-3/+3
* [AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih2017-11-021-0/+7
* [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0Jessica Paquette2017-09-011-2/+5
* Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner2017-08-231-5/+59
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-131-1/+39
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-111-7/+38
* fix trivial typos, NFCHiroshi Inoue2017-06-271-3/+3
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-06-061-4/+40
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-051-7/+35
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate within...Renato Golin2017-04-231-1/+2
* [APInt] Fix a few places that use APInt::getRawData to operate within the nor...Craig Topper2017-04-231-2/+1
* [MIR] Support Customed Register Mask and CSRsOren Ben Simhon2017-03-191-2/+32
* MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover2017-02-131-2/+40
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-12/+16
* MIRParser: Allow regclass specification on operandMatthias Braun2017-01-181-2/+69
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-221-3/+3
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-3/+0
* [MIRParser] Add parsing hex literals of arbitrary size as unsigned integersKrzysztof Parzyszek2016-12-161-13/+38
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-3/+6
* Move FrameInstructions from MachineModuleInfo to MachineFunctionMatthias Braun2016-11-301-7/+5
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-181-1/+2
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-151-0/+23
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-021-1/+1
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-121-9/+39
* MIRParser: allow types on registers with a RegBank.Tim Northover2016-10-111-1/+2
* MIRParser: generic register operands with typesMatthias Braun2016-10-111-1/+1
* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-111-43/+65
* [MIRParser] Delete dead code. NFCI.Davide Italiano2016-09-211-12/+0
* Don't create a SymbolTable in Function when the LLVMContext discards value na...Mehdi Amini2016-09-171-3/+3
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-5/+1
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