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path: root/llvm/lib/CodeGen/MIRParser/MILexer.h
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* [FPEnv] Invert sense of MIFlag::FPExcept flagUlrich Weigand2020-01-101-1/+1
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-081-0/+1
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-081-1/+0
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-0/+1
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-081-1/+0
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-0/+1
* [MIR] Add MIR parsing for heap alloc site instruction markersAmy Huang2019-11-051-0/+1
* GlobalISel: Change representation of shuffle masksMatt Arsenault2019-08-131-0/+2
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-051-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-12-181-0/+1
* [mir] Serialize DILocation inline when not possible to use a metadata referenceDaniel Sanders2018-12-131-0/+1
* Revert r347490 as it breaks address sanitizer buildsLuke Cheeseman2018-11-231-1/+0
* Revert r343341Luke Cheeseman2018-11-231-0/+1
* Revert r343317Luke Cheeseman2018-09-281-1/+0
* Reapply changes reverted by r343235Luke Cheeseman2018-09-281-0/+1
* Revert r343192 as an ubsan build is currently failingLuke Cheeseman2018-09-271-1/+0
* Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman2018-09-271-0/+1
* Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman2018-09-261-1/+0
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-261-0/+1
* Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg2018-09-261-1/+0
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-261-0/+1
* add IR flags to MIMichael Berg2018-09-111-0/+3
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-201-0/+1
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-161-0/+3
* [MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn2018-05-051-3/+0
* MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg2018-05-031-0/+7
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-1/+2
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-261-0/+1
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-091-0/+1
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-151-0/+8
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-1/+3
* [AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih2017-11-021-0/+1
* [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include W...Eugene Zelenko2017-09-271-5/+5
* Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner2017-08-231-0/+1
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-131-1/+2
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-111-1/+2
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-121-0/+1
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-1/+2
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+2
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-291-0/+1
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-261-0/+1
* GlobalISel: implement alloca instructionTim Northover2016-07-221-0/+1
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-0/+1
* MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun2016-03-281-1/+2
* [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ...Quentin Colombet2016-03-081-2/+2
* [MIR] Teach the parser how to parse complex types of generic machine instruct...Quentin Colombet2016-03-081-0/+2
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-211-1/+2
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-201-0/+1
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