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* [MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn2018-05-051-19/+0
| | | | | | | | | | | | | | | | Summary: The current code cannot handle register class names like 'i32', which is a valid register class name in WebAssembly. This patch removes special handling for integer/scalar/pointer type parsing and treats them as normal identifiers. Reviewers: thegameg Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45948 llvm-svn: 331586
* MachineInst support mapping SDNode fast math flags for support in Back End ↵Michael Berg2018-05-031-0/+7
| | | | | | | | | | | | | | | | | | code generation Summary: Machine Instruction flags for fast math support and MIR print support Reviewers: spatel, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D45781 llvm-svn: 331417
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-1/+13
| | | | llvm-svn: 328887
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-7/+16
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-261-0/+1
| | | | | | | | | | Add support for printing / parsing the addrspace of a MachineMemOperand. Fixes PR35970. Differential Revision: https://reviews.llvm.org/D42502 llvm-svn: 323521
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-101-1/+1
| | | | | | | | | | Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-091-0/+1
| | | | | | | | | We are printing / parsing the `frame-setup` MachineInstr flag but not the `frame-destroy` one. Differential Revision: https://reviews.llvm.org/D41509 llvm-svn: 322071
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-151-0/+8
| | | | | | | | | | | | | | | | | | | The following CFI directives are suported by MC but not by MIR: * .cfi_rel_offset * .cfi_adjust_cfa_offset * .cfi_escape * .cfi_remember_state * .cfi_restore_state * .cfi_undefined * .cfi_register * .cfi_window_save Add support for printing, parsing and update tests. Differential Revision: https://reviews.llvm.org/D41230 llvm-svn: 320819
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-0/+1
| | | | | | | | | | | | | | | | | | Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-0/+3
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih2017-11-021-0/+1
| | | | | | | | | | | | | | As of today we only use .cfi_offset to specify the offset of a CSR, but we never use .cfi_restore when the CSR is restored. If we want to perform a more advanced type of shrink-wrapping, we need to use .cfi_restore in order to switch the CFI state between blocks. This patch only aims at adding support for the directive. Differential Revision: https://reviews.llvm.org/D36114 llvm-svn: 317199
* [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include ↵Eugene Zelenko2017-09-271-6/+12
| | | | | | What You Use warnings; other minor fixes (NFC). llvm-svn: 314363
* Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner2017-08-231-0/+1
| | | | | | | | | | | | | | | | | | | Summary: Most DIExpressions are empty or very simple. When they are complex, they tend to be unique, so checking them inline is reasonable. This also avoids the need for CodeGen passes to append to the llvm.dbg.mir named md node. See also PR22780, for making DIExpression not be an MDNode. Reviewers: aprantl, dexonsmith, dblaikie Subscribers: qcolombet, javed.absar, eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37075 llvm-svn: 311594
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 introduces the notion of memory scopes in atomic operations to global and local memory. These scopes restrict how synchronization is achieved, which can result in improved performance. This change extends existing notion of synchronization scopes in LLVM to support arbitrary scopes expressed as target-specific strings, in addition to the already defined scopes (single thread, system). The LLVM IR and MIR syntax for expressing synchronization scopes has changed to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this replaces *singlethread* keyword), or a target-specific name. As before, if the scope is not specified, it defaults to CrossThread/System scope. Implementation details: - Mapping from synchronization scope name/string to synchronization scope id is stored in LLVM context; - CrossThread/System and SingleThread scopes are pre-defined to efficiently check for known scopes without comparing strings; - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in the bitcode. Differential Revision: https://reviews.llvm.org/D21723 llvm-svn: 307722
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-121-14/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D25530 llvm-svn: 284052
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-0/+1
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+2
| | | | llvm-svn: 278969
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-291-0/+1
| | | | | | | This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-261-2/+9
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-261-5/+5
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* GlobalISel: implement alloca instructionTim Northover2016-07-221-3/+7
| | | | llvm-svn: 276433
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-4/+6
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* Remove some unneeded headers and replace some headers with forward class ↵Mehdi Amini2016-04-161-0/+1
| | | | | | | | | | | declarations (NFC) Differential Revision: http://reviews.llvm.org/D19154 Patch by Eugene Kosov <claprix@yandex.ru> From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266524
* MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun2016-03-281-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D18279 llvm-svn: 264608
* MILexer: Add ErrorCallbackType typedef; NFCMatthias Braun2016-03-181-30/+22
| | | | llvm-svn: 263829
* [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ↵Quentin Colombet2016-03-081-2/+2
| | | | | | | | parser. Thanks to Ahmed Bougacha for noticing! llvm-svn: 262899
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-081-0/+4
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-211-0/+26
| | | | | | memory operands. llvm-svn: 245745
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-201-0/+1
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-191-0/+2
| | | | llvm-svn: 245521
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-191-0/+1
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-191-0/+1
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* MIR Serialization: Serialize the memory operand's range metadata node.Alex Lorenz2015-08-171-0/+1
| | | | llvm-svn: 245247
* MIR Serialization: Serialize the memory operand's noalias metadata node.Alex Lorenz2015-08-171-0/+1
| | | | llvm-svn: 245246
* MIR Serialization: Serialize the memory operand's alias scope metadata node.Alex Lorenz2015-08-171-0/+1
| | | | llvm-svn: 245245
* MIR Serialization: Serialize the memory operand's TBAA metadata node.Alex Lorenz2015-08-171-2/+29
| | | | llvm-svn: 245244
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-141-0/+1
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the 'internal' register operand flag.Alex Lorenz2015-08-141-0/+1
| | | | llvm-svn: 245085
* MIR Serialization: Serialize the bundled machine instructions.Alex Lorenz2015-08-141-0/+4
| | | | llvm-svn: 245082
* MIR Serialization: Change MIR syntax - use custom syntax for MBBs.Alex Lorenz2015-08-131-9/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit modifies the way the machine basic blocks are serialized - now the machine basic blocks are serialized using a custom syntax instead of relying on YAML primitives. Instead of using YAML mappings to represent the individual machine basic blocks in a machine function's body, the new syntax uses a single YAML block scalar which contains all of the machine basic blocks and instructions for that function. This is an example of a function's body that uses the old syntax: body: - id: 0 name: entry instructions: - '%eax = MOV32r0 implicit-def %eflags' - 'RETQ %eax' ... The same body is now written like this: body: | bb.0.entry: %eax = MOV32r0 implicit-def %eflags RETQ %eax ... This syntax change is motivated by the fact that the bundled machine instructions didn't map that well to the old syntax which was using a single YAML sequence to store all of the machine instructions in a block. The bundled machine instructions internally use flags like BundledPred and BundledSucc to determine the bundles, and serializing them as MI flags using the old syntax would have had a negative impact on the readability and the ease of editing for MIR files. The new syntax allows me to serialize the bundled machine instructions using a block construct without relying on the internal flags, for example: BUNDLE implicit-def dead %itstate, implicit-def %s1 ... { t2IT 1, 24, implicit-def %itstate %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate } This commit also converts the MIR testcases to the new syntax. I developed a script that can convert from the old syntax to the new one. I will post the script on the llvm-commits mailing list in the thread for this commit. llvm-svn: 244982
* MIR Serialization: Serialize the jump table pseudo source values.Alex Lorenz2015-08-121-0/+1
| | | | llvm-svn: 244813
* MIR Serialization: Serialize the GOT pseudo source values.Alex Lorenz2015-08-121-0/+1
| | | | llvm-svn: 244809
* MIR Serialization: Serialize the stack pseudo source values.Alex Lorenz2015-08-121-0/+1
| | | | llvm-svn: 244806
* MIR Serialization: Serialize the constant pool pseudo source values.Alex Lorenz2015-08-121-0/+1
| | | | llvm-svn: 244803
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-101-0/+1
| | | | llvm-svn: 244529
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-071-0/+1
| | | | llvm-svn: 244357
* MIR Parser: Simplify the token's string value handling.Alex Lorenz2015-08-061-24/+51
| | | | | | | | | | | | | | | | | This commit removes the 'StringOffset' and 'HasStringValue' fields from the MIToken struct and simplifies the 'stringValue' method which now returns the new 'StringValue' field. This commit also adopts a different way of initializing the lexed tokens - instead of constructing a new MIToken instance, the lexer resets the old token using the new 'reset' method and sets its attributes using the new 'setStringValue', 'setOwnedStringValue', and 'setIntegerValue' methods. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D11792 llvm-svn: 244295
* MIR Serialization: Serialize the 'invariant' machine memory operand flag.Alex Lorenz2015-08-061-0/+1
| | | | llvm-svn: 244230
* MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.Alex Lorenz2015-08-061-0/+1
| | | | llvm-svn: 244228
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-061-0/+1
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
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