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* GlobalISel: Fix RegBankSelect for REG_SEQUENCEMatt Arsenault2019-03-211-4/+16
| | | | | | | | | | | | | The AArch64 test was broken since the result register already had a set register class, so this test was a no-op. The mapping verify call would fail because the result size is not the same as the inputs like in a copy or phi. The AMDGPU testcases are half broken and introduce illegal VGPR->SGPR copies which need much more work to handle correctly (same for phis), but add them as a baseline. llvm-svn: 356713
* [GlobalISel] Include missing change from r356396Amara Emerson2019-03-181-4/+2
| | | | | | Forgot to add a change to relax some asserts in r356396. llvm-svn: 356411
* Revert r356304: remove subreg parameter from MachineIRBuilder::buildCopy()Amara Emerson2019-03-181-5/+5
| | | | | | | | | | | | | After review comments, it was preferred to not teach MachineIRBuilder about non-generic instructions beyond using buildInstr(). For AArch64 I've changed the buildCopy() calls to buildInstr() + a separate addReg() call. This also relaxes the MachineIRBuilder's COPY checking more because it may not always have a SrcOp given to it. llvm-svn: 356396
* [GlobalISel] Make isel verification checks of vregs run under NDEBUG only.Amara Emerson2019-03-161-4/+4
| | | | llvm-svn: 356309
* [GlobalISel] Allow MachineIRBuilder to build subregister copies.Amara Emerson2019-03-151-5/+5
| | | | | | | | | | | | This relaxes some asserts about sizes, and adds an optional subreg parameter to buildCopy(). Also update AArch64 instruction selector to use this in places where we previously used MachineInstrBuilder manually. Differential Revision: https://reviews.llvm.org/D59434 llvm-svn: 356304
* GlobalISel: Use multiple returns for intrinsic structsMatt Arsenault2019-03-142-16/+9
| | | | | | | | | | | This is consistent with what SelectionDAG does and is much easier to work with than the extract sequence with an artificial wide register. For the AMDGPU control flow intrinsics, this was producing an s128 for the i64, i1 tuple return. Any legalization that should apply to a real s128 value would badly obscure the direct values that need to be seen. llvm-svn: 356147
* [GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrsQuentin Colombet2019-03-142-10/+60
| | | | | | | | | | | | | | | | | | | getConstantVRegVal used to only look for G_CONSTANT when looking at unboxing the value of a vreg. However, constants are sometimes not directly used and are hidden behind trunc, s|zext or copy chain of computation. In particular this may be introduced by the legalization process that doesn't want to simplify these patterns because it can lead to infine loop when legalizing a constant. To circumvent that problem, add a new variant of getConstantVRegVal, named getConstantVRegValWithLookThrough, that allow to look through extensions. Differential Revision: https://reviews.llvm.org/D59227 llvm-svn: 356116
* [GlobalISel][AArch64] Always fall back on aarch64.neon.addp.*Jessica Paquette2019-03-111-7/+31
| | | | | | | | | | | | | | Overloaded intrinsics aren't necessarily safe for instruction selection. One such intrinsic is aarch64.neon.addp.*. This is a temporary workaround to ensure that we always fall back on that intrinsic. Eventually this will be replaced with a proper solution. https://bugs.llvm.org/show_bug.cgi?id=40968 Differential Revision: https://reviews.llvm.org/D59062 llvm-svn: 355865
* [MIPS GlobalISel] Silence uninitialized variable warningBenjamin Kramer2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | The control flow here cannot ever use the uninitialized value, but it's too hard for the compiler to figure that out. Clang warns: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: error: variable 'CarrySum' is used uninitialized whenever 'for' loop exits because its condition is false [-Werror,-Wsometimes-uninitialized] for (unsigned i = 2; i < Factors.size(); ++i) ^~~~~~~~~~~~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2604:26: note: uninitialized use occurs here CarrySumPrevDstIdx = CarrySum; ^~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: note: remove the condition if it is always true for (unsigned i = 2; i < Factors.size(); ++i) ^~~~~~~~~~~~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2583:22: note: initialize the variable 'CarrySum' to silence this warning unsigned CarrySum; ^ = 0 llvm-svn: 355818
* [MIPS GlobalISel] NarrowScalar G_UMULHPetar Avramovic2019-03-111-3/+9
| | | | | | | | | | NarrowScalar G_UMULH in LegalizerHelper using multiplyRegisters helper function. NarrowScalar G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58825 llvm-svn: 355815
* [MIPS GlobalISel] NarrowScalar G_MULPetar Avramovic2019-03-112-33/+87
| | | | | | | | | | | | | Narrow Scalar G_MUL for MIPS32. Revisit NarrowScalar implementation in LegalizerHelper. Introduce new helper function multiplyRegisters. It performs generic multiplication of values held in multiple registers. Generated instructions use only types NarrowTy and i1. Destination can be same or two times size of the source. Differential Revision: https://reviews.llvm.org/D58824 llvm-svn: 355814
* GlobalISel: Implement fewerElementsVector for phiMatt Arsenault2019-02-281-8/+85
| | | | llvm-svn: 355048
* GlobalISel: Implement moreElementsVector for phiMatt Arsenault2019-02-281-0/+21
| | | | llvm-svn: 355047
* [MIPS GlobalISel] Select G_UADDOPetar Avramovic2019-02-261-0/+12
| | | | | | | | | Lower G_UADDO. Legalize G_UADDO for MIPS32 Differential Revision: https://reviews.llvm.org/D58671 llvm-svn: 354900
* RegBankSelect: Handle slightly more complex value mappingsMatt Arsenault2019-02-251-12/+16
| | | | | | | | Try to use concat_vectors. Also remove unnecessary assert on pointers. Fixes asserting for <4 x s16> operations and 64-bit pointers for AMDGPU. llvm-svn: 354828
* RegBankSelect: Allow targets to introduce control flow for mappingMatt Arsenault2019-02-211-0/+13
| | | | | | | | | | | | | For AMDGPU, if an operand requires an SGPR but is only available as a VGPR, a loop needs to be introduced to execute the instruction with each unique combination of values across all lanes. The rest of the instructions in the block will be moved to a new block following the loop. Check if the next instruction's parent changed, and update the iterators and insertion block if this happened. Tests will be included in a future patch. llvm-svn: 354591
* GlobalISel: Fix fewerElementsVector for ctlz with different result typeMatt Arsenault2019-02-201-1/+5
| | | | | | Also complete the set of related operations. llvm-svn: 354480
* GlobalISel: Implement moreElementsVector for g_insert resultsMatt Arsenault2019-02-201-0/+8
| | | | llvm-svn: 354477
* GlobalISel: Implement moreElementsVector for selectMatt Arsenault2019-02-191-0/+12
| | | | llvm-svn: 354354
* GlobalISel: Implement moreElementsVector for G_EXTRACT sourceMatt Arsenault2019-02-191-0/+7
| | | | llvm-svn: 354348
* GlobalISel: Implement moreElementsVector for bit opsMatt Arsenault2019-02-191-0/+40
| | | | llvm-svn: 354345
* [GlobalISel][AArch64] Legalize + select some llvm.ctlz.* intrinsicsJessica Paquette2019-02-181-0/+1
| | | | | | | | | | | | Legalize/select llvm.ctlz.* Add select-ctlz to show that we actually select them. Update arm64-clrsb.ll and arm64-vclz.ll to show that we perform valid transformations in optimized builds, and document where GISel can improve. Differential Revision: https://reviews.llvm.org/D58155 llvm-svn: 354299
* GlobalISel: Implement widenScalar for g_extract scalar resultsMatt Arsenault2019-02-181-6/+48
| | | | llvm-svn: 354293
* GlobalISel: Make buildExtract use DstOp/SrcOpMatt Arsenault2019-02-181-12/+15
| | | | llvm-svn: 354292
* GlobalISel: Fix double count of offset for irregular vector breakdownsMatt Arsenault2019-02-181-1/+0
| | | | | | | Fixes cases with odd vectors that break into multiple requested size pieces. llvm-svn: 354280
* [GISel][NFC]: Add methods to speed up insertion into GISelWorklistAditya Nandakumar2019-02-152-3/+6
| | | | | | | | | | | | | https://reviews.llvm.org/D58073 Speed up insertion during the initial populating phase into the GISelWorkList by deferring repeatedly resizing the DenseMap. This results in ~10% improvement in the combiner passes, and ~3% speedup in the Legalizer. reviewed by: aemerson. llvm-svn: 354093
* GlobalISel: Add alignment to LegalityQuery MMOsMatt Arsenault2019-02-142-10/+15
| | | | | | | This allows targets to specify the minimum alignment required for the load/store. llvm-svn: 354071
* [MIPS GlobalISel] Select branch instructionsPetar Avramovic2019-02-141-1/+1
| | | | | | | | | | | | | Select G_BR and G_BRCOND for MIPS32. Unconditional branch G_BR does not have register operand, for that reason we only add tests. Since conditional branch G_BRCOND compares register to zero on MIPS32, explicit extension must be performed on i1 condition in order to set high bits to appropriate value. Differential Revision: https://reviews.llvm.org/D58182 llvm-svn: 354022
* [globalisel][combine] Split existing rules into a match and apply stepDaniel Sanders2019-02-141-21/+39
| | | | | | | | | | | | | | | | | | | Summary: The declarative tablegen definitions split rules into match and apply steps. Prepare for that by doing the same in the C++ implementations. This aids some of the migration effort while the tablegen version is incomplete. Reviewers: bogner, volkan, aditya_nandakumar, paquette, aemerson Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, Petar.Avramovic, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58150 llvm-svn: 353996
* [GlobalISel][NFC] Gardening: Make translateSimpleUnaryIntrinsic generalJessica Paquette2019-02-121-26/+18
| | | | | | | | | | | | | | Instead of only having this code work for unary intrinsics, have it work for an arbitrary number of parameters. Factor out the cases that fall under this (fma, pow). This makes it a bit easier to add more intrinsics which don't require any special work. Differential Revision: https://reviews.llvm.org/D58079 llvm-svn: 353863
* [GlobalISel][AArch64] Select llvm.bswap* for non-vector typesJessica Paquette2019-02-121-0/+2
| | | | | | | | | | | | | | | | This teaches the IRTranslator to emit G_BSWAP when it runs into Intrinsic::bswap. This allows us to select G_BSWAP for non-vector types in AArch64. Add a select-bswap.mir test, and add global isel checks to a couple existing tests in test/CodeGen/AArch64. This doesn't handle every bswap case, since some of these rely on known bits stuff. This just lets us handle the naive case. Differential Revision: https://reviews.llvm.org/D58081 llvm-svn: 353861
* GlobalISel: Use default rounding mode when extending fconstantMatt Arsenault2019-02-121-3/+8
| | | | | | | I don't think this matters since the values should all be exactly representable. llvm-svn: 353844
* GlobalISel: Move some more legalize cases into functionsMatt Arsenault2019-02-121-165/+190
| | | | llvm-svn: 353843
* GlobalISel: Implement moreElementsVector for implicit_defMatt Arsenault2019-02-111-0/+29
| | | | llvm-svn: 353754
* GlobalISel: Fix not calling the observer when legalizing G_EXTRACTMatt Arsenault2019-02-111-0/+2
| | | | llvm-svn: 353750
* [globalisel] Correct string emitted by GISelChangeObserver::erasingInstr()Daniel Sanders2019-02-111-1/+1
| | | | | | The API indicates that the MI is about to be erased rather than it has been erased. llvm-svn: 353746
* [GlobalISel][AArch64] Select G_FFLOORJessica Paquette2019-02-111-0/+2
| | | | | | | | | | | This teaches the legalizer about G_FFLOOR, and lets us select G_FFLOOR in AArch64. It updates the existing floating point tests, and adds a select-floor.mir test. Differential Revision: https://reviews.llvm.org/D57486 llvm-svn: 353722
* Recommit "[GlobalISel] Add IRTranslator support for G_FFLOOR"Jessica Paquette2019-02-111-0/+2
| | | | | | | | | After the changes introduced in r353586, this instruction doesn't cause any issues for any backend. Original review: https://reviews.llvm.org/D57485 llvm-svn: 353720
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-112-0/+4
| | | | llvm-svn: 353719
* Re-apply r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-082-9/+10
| | | | | | | | CSEMIRBuilder" With a fix after r353563 that adds some more opcodes. llvm-svn: 353579
* Revert r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-082-10/+9
| | | | | | | | | | | | CSEMIRBuilder" This reverts commit r353553. This breaks CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/57963/console llvm-svn: 353575
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch accompanies the RFC posted here: http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html This patch adds a new CallBr IR instruction to support asm-goto inline assembly like gcc as used by the linux kernel. This instruction is both a call instruction and a terminator instruction with multiple successors. Only inline assembly usage is supported today. This also adds a new INLINEASM_BR opcode to SelectionDAG and MachineIR to represent an INLINEASM block that is also considered a terminator instruction. There will likely be more bug fixes and optimizations to follow this, but we felt it had reached a point where we would like to switch to an incremental development model. Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii Differential Revision: https://reviews.llvm.org/D53765 llvm-svn: 353563
* [GISel][NFC]: Add missing call to record CSE hits in the CSEMIRBuilderAditya Nandakumar2019-02-082-9/+10
| | | | | | | | | | https://reviews.llvm.org/D57932 Add some logging + tests to make sure CSEInfo prints debug output. reviewed by: arsenm llvm-svn: 353553
* [MIPS GlobalISel] Select any extending load and truncating storePetar Avramovic2019-02-081-7/+0
| | | | | | | | | | | | | | | | | | Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
* AMDGPU/GlobalISel: Legalize addrspacecastMatt Arsenault2019-02-081-0/+1
| | | | | | | Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
* GlobalISel: Try to fix bot failuresMatt Arsenault2019-02-071-5/+5
| | | | | | Don't rely on order of evaluation of function arguments. llvm-svn: 353460
* GlobalISel: Implement narrowScalar for shift main typeMatt Arsenault2019-02-072-12/+235
| | | | | | | | | | | | | | | This is pretty much directly ported from SelectionDAG. Doesn't include the shift by non-constant but known bits version, since there isn't a globalisel version of computeKnownBits yet. This shows a disadvantage of targets not specifically which type should be used for the shift amount. If type 0 is legalized before type 1, the operations on the shift amount type use the wider type (which are also less likely to legalize). This can be avoided by targets specifying legalization actions on type 1 earlier than for type 0. llvm-svn: 353455
* GlobalISel: Implement fewerElementsVector for shiftsMatt Arsenault2019-02-071-30/+130
| | | | | | | | | Introduce a new function which handles instructions with multiple type indices, but have the same number of vector elements. Also legalize v2s16 shifts when applicable. llvm-svn: 353432
* GlobalISel: Try to make legalize rules more useful for vectorsMatt Arsenault2019-02-072-10/+49
| | | | | | | Mostly keep the existing functions on scalars, but add versions which also operate based on the vector element size. llvm-svn: 353430
* Move IR flag handling directly into builder calls for cases translated from ↵Michael Berg2019-02-061-32/+30
| | | | | | | | | | | | | | Instructions in GlobalIsel Reviewers: aditya_nandakumar, volkan Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, volkan, Petar.Avramovic Differential Revision: https://reviews.llvm.org/D57630 llvm-svn: 353336
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