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path: root/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
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* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-11/+11
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
* [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar2018-02-021-13/+5
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-131-1/+0
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-4/+4
* [RegisterBankInfo] Relax the assert of having matching type sizes on default ...Quentin Colombet2017-11-181-1/+5
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-4/+4
* [RegisterBankInfo] Cache the getMinimalPhysRegClass informationQuentin Colombet2017-10-131-5/+19
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-4/+4
* CodeGen: Minor cleanups to use MachineInstr::getMF. NFCJustin Bogner2017-10-101-5/+5
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-051-15/+53
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+1
* [RegBankSelect] Support REG_SEQUENCE for generic mappingQuentin Colombet2017-04-011-8/+18
* [GlobalISel] Ignore %noreg when applying default regbank mapping.Ahmed Bougacha2017-03-071-0/+7
* unique_ptrify some containers in GlobalISel::RegisterBankInfoDavid Blaikie2017-01-301-19/+9
* [RegisterBankInfo] Emit proper type for remapped registers.Quentin Colombet2017-01-281-3/+25
* Cleanup dump() functions.Matthias Braun2017-01-281-0/+8
* Fix memory leak in globalisel.Evgeniy Stepanov2017-01-281-0/+2
* [globalisel] Move as much RegisterBank initialization to the constructor as p...Daniel Sanders2017-01-121-12/+3
* [globalisel] Initialize RegisterBanks with static data.Daniel Sanders2017-01-121-100/+8
* GlobalISel: only print debug info with -debug. NFC.Tim Northover2017-01-111-1/+1
* [globalisel] Stop requiring -debug/-debug-only=registerbankinfo for assertions.Daniel Sanders2017-01-061-6/+7
* [RegisterBankInfo] Allow to set a register class when nothing else is setQuentin Colombet2016-12-221-3/+2
* GlobalISel: Fix indentation. NFCDiana Picus2016-11-141-3/+3
* GlobalISel: fix typo. NFCTim Northover2016-11-091-2/+2
* [RegisterBankInfo] Change the default mapping for Copy and PHI.Quentin Colombet2016-09-291-52/+35
* [RegisterBankInfo] Uniquely generate OperandsMapping.Quentin Colombet2016-09-281-8/+63
* [RegisterBankInfo] Rework the APIs of ValueMapping.Quentin Colombet2016-09-281-10/+12
* [RegisterBankInfo] Constify the member of the XXXMapping maps.Quentin Colombet2016-09-241-2/+2
* [RegisterBankInfo] Add statistics for dynamic value mappings.Quentin Colombet2016-09-241-0/+8
* [RegisterBankInfo] Uniquely generate ValueMapping.Quentin Colombet2016-09-241-11/+52
* [RegisterBankInfo] Keep valid pointers for PartialMappings.Quentin Colombet2016-09-241-4/+9
* [RegisterBankInfo] Add statistics for dynamic partial mappings.Quentin Colombet2016-09-231-0/+11
* [RegisterBankInfo] Mark the dump methods with LLVM_DUMP_METHOD.Quentin Colombet2016-09-231-4/+4
* [RegisterBankInfo] Check that the mapping covers the interesting bits.Quentin Colombet2016-09-231-2/+3
* [RegisterBankInfo] Use array instead of SmallVector for BreakDown.Quentin Colombet2016-09-231-32/+34
* [RegisterBankInfo] Move to statically allocated RegisterBank.Quentin Colombet2016-09-221-3/+8
* [RegisterBankInfo] Take advantage of the extra argument of SmallVector::resize.Quentin Colombet2016-09-221-3/+1
* [RegisterBankInfo] Adapt call to std::fill due to use of SmallVector.Quentin Colombet2016-09-191-1/+1
* [RegisterBankInfo] Avoid heap allocation in most cases.Quentin Colombet2016-09-191-1/+1
* [AArch64][GlobalISel] Test default regbank mapping for G_ICMP.Ahmed Bougacha2016-09-161-1/+1
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-1/+1
* GlobalISel: remove G_TYPE and G_PHITim Northover2016-09-091-2/+1
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-2/+3
* GlobalISel: use G_TYPE to annotate physregs with a type.Tim Northover2016-08-311-1/+2
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+19
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-33/+13
* [GlobalISel] Simplify more RegClassOrRegBank is+get. NFC.Ahmed Bougacha2016-07-191-5/+3
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