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* Fix gcc -Wparentheses warning. NFCI.Simon Pilgrim2019-01-251-2/+2
| | | | llvm-svn: 352191
* RegBankSelect: Fix use after free in r352123Matt Arsenault2019-01-241-1/+1
| | | | llvm-svn: 352130
* RegBankSelect: Support some more complex part mappingsMatt Arsenault2019-01-241-25/+74
| | | | llvm-svn: 352123
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [GlobalISel] Fix unused variable warning in Release builds.Benjamin Kramer2019-01-081-3/+3
| | | | llvm-svn: 350618
* Fix typosMatt Arsenault2019-01-081-2/+2
| | | | llvm-svn: 350597
* RegBankSelect: Fix copy insertion point for terminatorsMatt Arsenault2019-01-081-9/+15
| | | | | | | | | | | | | | | If a copy was needed to handle the condition of brcond, it was being inserted before the defining instruction. Add tests for iterator edge cases. I find the existing code here suspect for the case where it's looking for terminators that modify the register. It's going to insert a copy in the middle of the terminators, which isn't allowed (it might be necessary to have a COPY_terminator if anybody actually needs this). Also legalize brcond for AMDGPU. llvm-svn: 350595
* GlobalISel: Improve crash on invalid mappingMatt Arsenault2018-12-181-1/+1
| | | | | | | | If NumBreakDowns is 0, BreakDown is null. This trades a null dereference with an assert somewhere else. llvm-svn: 349464
* ADT/STLExtras: Introduce llvm::empty; NFCMatthias Braun2018-10-311-1/+1
| | | | | | | | This is modeled after C++17 std::empty(). Differential Revision: https://reviews.llvm.org/D53909 llvm-svn: 345679
* [RegisterBankInfo] Ignore InstrMappings that create impossible to repair ↵Tom Stellard2018-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | operands Summary: This is a follow-up to r303043. In computeMapping(), we need to disqualify an InstrMapping if it would be impossible to repair one of the registers in the instruction to match the mapping. This change is needed in order to be able to define an instruction mapping for G_SELECT for the AMDGPU target and will be tested by test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir Reviewers: ab, qcolombet, t.p.northover, dsanders Reviewed By: qcolombet Subscribers: tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D49735 llvm-svn: 337882
* CodeGen: Remove pipeline dependencies on StackProtector; NFCMatthias Braun2018-07-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r336929 with a fix to accomodate for the Mips target scheduling multiple SelectionDAG instances into the pass pipeline. PrologEpilogInserter and StackColoring depend on the StackProtector analysis being alive from the point it is run until PEI, which requires that they are all scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass between StackProtector and PEI results in these passes being in separate FunctionPassManagers and the StackProtector is not available for PEI. PEI and StackColoring don't use much information from the StackProtector pass, so transfering the required information to MachineFrameInfo is cleaner than keeping the StackProtector pass around. This commit moves the SSP layout information to MFI instead of keeping it in the pass. This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587) is a first draft of the pagerando implementation described in http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html. Patch by Stephen Crane <sjc@immunant.com> Differential Revision: https://reviews.llvm.org/D49256 llvm-svn: 336964
* Revert "(HEAD -> master, origin/master, arcpatch-D37582) CodeGen: Remove ↵Matthias Braun2018-07-121-1/+0
| | | | | | | | | | pipeline dependencies on StackProtector; NFC" This was triggering pass scheduling failures. This reverts commit r336929. llvm-svn: 336934
* CodeGen: Remove pipeline dependencies on StackProtector; NFCMatthias Braun2018-07-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | PrologEpilogInserter and StackColoring depend on the StackProtector analysis being alive from the point it is run until PEI, which requires that they are all scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass between StackProtector and PEI results in these passes being in separate FunctionPassManagers and the StackProtector is not available for PEI. PEI and StackColoring don't use much information from the StackProtector pass, so transfering the required information to MachineFrameInfo is cleaner than keeping the StackProtector pass around. This commit moves the SSP layout information to MFI instead of keeping it in the pass. This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587) is a first draft of the pagerando implementation described in http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html. Patch by Stephen Crane <sjc@immunant.com> Differential Revision: https://reviews.llvm.org/D49256 llvm-svn: 336929
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-22/+22
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See r331124 for how I made a list of files missing the include. I then ran this Python script: for f in open('filelist.txt'): f = f.strip() fl = open(f).readlines() found = False for i in xrange(len(fl)): p = '#include "llvm/' if not fl[i].startswith(p): continue if fl[i][len(p):] > 'Config': fl.insert(i, '#include "llvm/Config/llvm-config.h"\n') found = True break if not found: print 'not found', f else: open(f, 'w').write(''.join(fl)) and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p` and tried to fix include ordering and whatnot. No intended behavior change. llvm-svn: 331184
* [GlobalISel][AArch64] Adding -disable-gisel-legality-check CL optionRoman Tereshin2018-03-011-13/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently it's impossible to test InstructionSelect pass with MIR which is considered illegal by the Legalizer in Assert builds. In early stages of porting an existing backend from SelectionDAG ISel to GlobalISel, however, we would have very basic CallLowering, Legalizer, and RegBankSelect implementations, but rather functional Instruction Select with quite a few patterns selectable due to the semi-automatic porting process borrowing them from SelectionDAG ISel. As we are trying to define legality as a property of being selectable by the instruction selector, it would be nice to be able to easily check what the selector can do in its current state w/o the legality check provided by the Legalizer getting in the way. It also seems beneficial to have a regression testing set up that would not allow the selector to silently regress in its support of the MIR not supported yet by the previous passes in the GlobalISel pipeline. This commit adds -disable-gisel-legality-check command line option to llc that disables those legality checks in RegBankSelect and InstructionSelect passes. It also adds quite a few MIR test cases for AArch64's Instruction Selector. Every one of them would fail on the legality check at the moment, but will select just fine if the check is disabled. Every test MachineFunction is intended to exercise a specific selection rule and that rule only, encoded in the MachineFunction's name by the rule's number, ID, and index of its GIM_Try opcode in TableGen'erated MatchTable (-optimize-match-table=false). Reviewers: ab, dsanders, qcolombet, rovka Reviewed By: bogner Subscribers: kristof.beyls, volkan, aditya_nandakumar, aemerson, rengolin, t.p.northover, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D42886 llvm-svn: 326396
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-1/+1
| | | | | | | | | | | LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-4/+4
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-151-1/+1
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [RegisterBankInfo] Cache the getMinimalPhysRegClass informationQuentin Colombet2017-10-131-3/+2
| | | | | | | | | | | | | | | TargetRegisterInfo::getMinimalPhysRegClass is actually pretty expensive because it has to iterate over all the register classes. Cache this information as we need and get it so that we limit its usage. Right now, we heavily rely on it, because this is how we get the mapping for vregs defined by copies from physreg (i.e., the one that are ABI related). Improve compile time by up to 10% for that pass. NFC llvm-svn: 315759
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* GlobalISel: verify that a COPY is trivial when created.Tim Northover2017-06-271-3/+7
| | | | | | | | | | | | Without this check, COPY instructions can actually be one of the generic casts in disguise. That's confusing and bad. At some point during ISel this restriction has to be relaxed since the fully selected instructions will usually use COPY for those purposes. Right now I think it's possible that relaxation occurs during RegBankSelect (hence the change there). I'm not convinced that's where it belongs long-term though. llvm-svn: 306470
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-261-15/+32
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306341
* [RegisterBankInfo] Remove overly-agressive assertsTom Stellard2017-05-151-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: We were asserting in RegisterBankInfo if RBI.copyCost() returns UINT_MAX. This is OK for RegBankSelect::Mode::Fast since we only try one instruction mapping and can't recover from this, but for RegBankSelect::Mode::Greedy we will be considering multiple instruction mappings, so we can recover if we see a UNIT_MAX copy cost. The copy cost for one pair of register banks in the AMDGPU backend will be UNIT_MAX, so this patch will prevent AMDGPU tests from breaking. Reviewers: ab, qcolombet, t.p.northover, dsanders Reviewed By: qcolombet Subscribers: tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D33144 llvm-svn: 303043
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-051-13/+15
| | | | | | | | | | This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
* [GlobalISel] Emit opt remarks on isel fallbacks.Ahmed Bougacha2017-02-231-14/+9
| | | | | | | | | | | | | | | | | Having more fine-grained information on the specific construct that caused us to fallback is valuable for large-scale data collection. We still have the fallback warning, that's also used for FastISel. We still need to remove the fallback warning, and teach FastISel to also emit remarks (it currently has a combination of the warning, stats, and debug prints: the remarks could unify all three). The abort-on-fallback path could also be better handled using remarks: one could imagine a "-Rpass-error", analoguous to "-Werror", which would promote missed/failed remarks to errors. It's not clear whether that would be useful for other remarks though, so we're not there yet. llvm-svn: 296013
* Cleanup dump() functions.Matthias Braun2017-01-281-1/+3
| | | | | | | | | | | | | | | | | | We had various variants of defining dump() functions in LLVM. Normalize them (this should just consistently implement the things discussed in http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html For reference: - Public headers should just declare the dump() method but not use LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - The definition of a dump method should look like this: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MyClass::dump() { // print stuff to dbgs()... } #endif llvm-svn: 293359
* [RegBankSelect] Improve the output of the debug messages.Quentin Colombet2017-01-111-7/+32
| | | | | | Add more information about mapping cost and chosen solution. llvm-svn: 291629
* GlobalISel: handle G_SEQUENCE fallbacks gracefully.Tim Northover2016-12-061-0/+3
| | | | | | | | | | There were two problems: + AArch64 was reusing random data from its binary op tables, which is complete nonsense for G_SEQUENCE. + Even when AArch64 gave up and said it couldn't handle G_SEQUENCE, the generic code asserted. llvm-svn: 288836
* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-3/+3
| | | | | | | | | | The previous names were both misleading (the MachineLegalizer actually contained the info tables) and inconsistent with the selector & translator (in having a "Machine") prefix. This should make everything sensible again. The only functional change is the name of a couple of command-line options. llvm-svn: 284287
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* [RegisterBankInfo] Change the default mapping for Copy and PHI.Quentin Colombet2016-09-291-2/+2
| | | | | | | | | | | | | | Instead of producing a mapping for all the operands, we only generate a mapping for the definition. Indeed, the other operands are not constrained by the instruction and thus, we should leave the choice to the actual definition to do the right thing. In pratice this is almost NFC, but with one advantage. We will have only one instance of OperandsMapping for each copy and phi that map to one register bank instead of one different instance for each different number of operands for each copy and phi. llvm-svn: 282756
* [RegBankSelect] Use DEBUG_TYPE instead of repeating the name of the passQuentin Colombet2016-09-231-2/+2
| | | | | | NFC llvm-svn: 282267
* [RegisterBankInfo] Use array instead of SmallVector for BreakDown.Quentin Colombet2016-09-231-10/+8
| | | | | | | | | | | | | This is another step toward TableGen'ed like structures. The BreakDown of the mapping of the value will be statically computed by TableGen, thus we only have to point to the right entry in the table instead of dynamically allocate the mapping for each instruction. We still support the dynamic allocation through a factory of PartialMapping to ease the bring-up of the targets while the TableGen backend is not available. llvm-svn: 282213
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-1/+2
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* [RegBankSelect] Do not abort when the target wants to fall back.Quentin Colombet2016-08-271-17/+48
| | | | llvm-svn: 279906
* [GlobalISel] Teach the core pipeline not to run if ISel failed.Quentin Colombet2016-08-271-0/+5
| | | | llvm-svn: 279889
* [GlobalISel] Set, require, and verify Legalized MF property.Ahmed Bougacha2016-08-021-0/+21
| | | | | | | | | | | | | RegBankSelect and InstructionSelect run after the legalizer and require a Legalized function: check that all instructions are legal. Note that this should be in the MachineVerifier, but it can't use the MachineLegalizer as it's currently in the separate GlobalISel library. Note that the RegBankSelect verifier checks have the same layering problem, but we only use inline methods so end up not needing to link against the GlobalISel library. llvm-svn: 277472
* [GlobalISel] Don't RegBankSelect target-specific instructions.Ahmed Bougacha2016-08-021-1/+7
| | | | | | They don't have types and should be using register classes. llvm-svn: 277447
* GlobalISel: add specialized buildCopy function to MachineInstrBuilder.Tim Northover2016-07-261-1/+1
| | | | | | NFC. llvm-svn: 276763
* GlobalISel: remove redundant ';'s. NFCTim Northover2016-07-261-1/+1
| | | | llvm-svn: 276723
* [RegBankSelect] Print out the actual mapping of the operands.Quentin Colombet2016-06-081-0/+1
| | | | | | This improves the debuggability of the pass. llvm-svn: 272210
* [RegBankSelect] Remove a debug print of a potentially dead instruction.Quentin Colombet2016-06-081-2/+2
| | | | | | | | For complex rewrittings, which do not occur currently, the related machine instruction may have been deleted in the process. Therefore, do not try to print it after the mapping is applied. llvm-svn: 272209
* [RegBankSelect] Silence an unused variable warning in release mode.Quentin Colombet2016-06-081-0/+1
| | | | llvm-svn: 272177
* [RegBankSelect] Comment on how we could improve repairing with copies.Quentin Colombet2016-06-081-0/+11
| | | | | | | | | | | When repairing with a copy, instead of accounting for the cost of that copy and actually inserting it, we may be able to use an alternative source for the register to repair and just use it. Make sure this is documented, so that we consider that opportunity at some point. llvm-svn: 272176
* [RegBankSelect] Use RegisterBankInfo applyMapping method.Quentin Colombet2016-06-081-11/+8
| | | | | | | The RegBankSelect pass can now rely on the target to do the remapping of the instructions. llvm-svn: 272169
* [RegBankSelect] Use the OperandMapper class to hold remap information.Quentin Colombet2016-06-081-10/+8
| | | | | | | | | Now that we have an entity that hold the remap information the rewritting should be easier to do. No functional changes. llvm-svn: 272164
* [RegBankSelect] Use const_iterator instead of iterator for repairReg.Quentin Colombet2016-06-081-1/+1
| | | | | | | The repairing code has no reason to change the source or destination of the registers. llvm-svn: 272163
* [RegBankSelect] Introduce a command line option to override the running mode.Quentin Colombet2016-06-081-0/+14
| | | | | | | | | | When the command line option is set, it overrides any thing that the target may have set. The rationale is that we get what we asked for. Options are respectively regbankselect-fast and regbankselect-greedy for fast and greedy mode. llvm-svn: 272158
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