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path: root/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
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* [GISEL]: Move getConstantVReg to UtilsAditya Nandakumar2017-04-191-17/+0
| | | | | | NFCI llvm-svn: 300751
* [tablegen][globalisel] Add support for nested instruction matching.Daniel Sanders2017-04-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
* [GlobalISel] Add a 'getConstantVRegVal' helper.Ahmed Bougacha2017-03-271-12/+20
| | | | | | Use it to compare immediate operands. llvm-svn: 298855
* [GlobalISel] Move method definition to the proper file. NFC.Ahmed Bougacha2017-03-191-0/+21
| | | | llvm-svn: 298221
* [X86][GlobalISel] Initial implementation , select G_ADD gpr, gprIgor Breger2017-02-221-0/+7
| | | | | | | | | | | | | | Summary: Initial implementation for X86InstructionSelector. Handle selection COPY and G_ADD/G_SUB gpr, gpr . Reviewers: qcolombet, rovka, zvi, ab Reviewed By: rovka Subscribers: mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29816 llvm-svn: 295824
* [GlobalISel] Refactor the logic to constraint registers.Quentin Colombet2016-12-221-12/+7
| | | | | | | | Move the logic to constraint register from InstructionSelector to a utility function. It will be required by other passes in the GlobalISel pipeline. llvm-svn: 290374
* [ARM] GlobalISel: Select add i32, i32Diana Picus2016-12-161-0/+5
| | | | | | | | | | | | | Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-101-2/+2
| | | | llvm-svn: 283809
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+4
| | | | llvm-svn: 278810
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-161-2/+2
| | | | | | And mark it as legal. llvm-svn: 278802
* [AArch64][GlobalISel] Select G_LOAD/G_STORE.Ahmed Bougacha2016-07-291-2/+6
| | | | | | | | | | Mostly straightforward as we ignore addressing modes and just use the base + unsigned immediate offset (always 0) variants. This currently fails to select extloads because we have yet to agree on a representation. llvm-svn: 277171
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+52
And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
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