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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-16 14:37:46 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-08-16 14:37:46 +0000 |
| commit | e4c03abddd29ebd10449dd5991f2d2f20c1cd771 (patch) | |
| tree | 89aa2028fdce3de80e495b42adee9c23ad7ec838 /llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp | |
| parent | 329a1fea32d8f626bf991815058764c9881a9ddd (diff) | |
| download | bcm5719-llvm-e4c03abddd29ebd10449dd5991f2d2f20c1cd771.tar.gz bcm5719-llvm-e4c03abddd29ebd10449dd5991f2d2f20c1cd771.zip | |
[AArch64][GlobalISel] Select G_MUL.
llvm-svn: 278810
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp index d508d1ee623..9d2630f2fca 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp @@ -39,6 +39,10 @@ bool InstructionSelector::constrainSelectedInstRegOperands( DEBUG(dbgs() << "Converting operand: " << MO << '\n'); assert(MO.isReg() && "Unsupported non-reg operand"); + // Physical registers don't need to be constrained. + if (TRI.isPhysicalRegister(MO.getReg())) + continue; + const TargetRegisterClass *RC = TII.getRegClass(I.getDesc(), OpI, &TRI, MF); assert(RC && "Selected inst should have regclass operand"); |
