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path: root/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
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* CodeGen: Use MachineInstr& in AntiDepBreaker API, NFCDuncan P. N. Exon Smith2016-02-271-27/+27
| | | | | | | | Take parameters as MachineInstr& instead of MachineInstr* in AntiDepBreaker API, since these are required to be non-null. No functionality change intended. Looking toward PR26753. llvm-svn: 262145
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-5/+4
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* MachineBasicBlock: Factor out common code into isReturnBlock()Matthias Braun2015-09-251-1/+1
| | | | llvm-svn: 248617
* Save LaneMask with livein registersMatthias Braun2015-09-091-2/+2
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-3/+2
| | | | llvm-svn: 245895
* MachineFrameInfo: Simplify pristine register calculation.Matthias Braun2015-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | About pristine regsiters: Pristine registers "hold a value that is useless to the current function, but that must be preserved - they are callee saved registers that have not been saved." This concept saves compile time as it frees the prologue/epilogue inserter from adding every such register to every basic blocks live-in list. However the current code in getPristineRegs is formulated in a complicated way: Inside the function prologue and epilogue all callee saves are considered pristine, while in the rest of the code only the non-saved ones are considered pristine. This requires logic to differentiate between prologue/epilogue and the rest and in the presence of shrink-wrapping this even becomes complicated/expensive. It's also unnecessary because the prologue epilogue inserters already mark callee-save registers that are saved/restores properly in the respective blocks in the prologue/epilogue (see updateLiveness() in PrologueEpilogueInserter.cpp). So only declaring non-saved/restored callee saved registers as pristine just works. Differential Revision: http://reviews.llvm.org/D10101 llvm-svn: 238524
* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* critical-anti-dependency breaker: don't use reg def info from kill insts ↵Sanjay Patel2014-08-201-2/+17
| | | | | | | | | | | | | | | | | | (PR20308) In PR20308 ( http://llvm.org/bugs/show_bug.cgi?id=20308 ), the critical-anti-dependency breaker caused a miscompile because it broke a WAR hazard using a register that it thinks is available based on info from a kill inst. Until PR18663 is solved, we shouldn't use any def/use info from a kill because they are really just nops. This patch adds guard checks for kills around calls to ScanInstruction() where the DefIndices array is set. For good measure, add an assert in ScanInstruction() so we don't hit this bug again. The test case is a reduced version of the code from the bug report. Differential Revision: http://reviews.llvm.org/D4977 llvm-svn: 216114
* use register iterators that include self to reduce code duplication in ↵Sanjay Patel2014-08-061-25/+6
| | | | | | | | | | | | | | | | CriticalAntiDepBreaker This patch addresses 2 FIXME comments that I added to CriticalAntiDepBreaker while fixing PR20020. Initialize an MCSubRegIterator and an MCRegAliasIterator to include the self reg. Assuming that works as advertised, there should be functional difference with this patch, just less code. Also, remove the associated asserts - we're setting those values just before, so the asserts don't do anything meaningful. Differential Revision: http://reviews.llvm.org/D4566 llvm-svn: 214973
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-5/+4
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-11/+9
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* bug fix for PR20020: anti-dependency-breaker causes miscompilationSanjay Patel2014-07-031-0/+31
| | | | | | | | | | | | | This patch sets the 'KeepReg' bit for any tied and live registers during the PrescanInstruction() phase of the dependency breaking algorithm. It then checks those 'KeepReg' bits during the ScanInstruction() phase to avoid changing any tied registers. For more details, please see comments in: http://llvm.org/bugs/show_bug.cgi?id=20020 I added two FIXME comments for code that I think can be removed by using register iterators that include self. I don't want to include those code changes with this patch, however, to keep things as small as possible. The test case is larger than I'd like, but I don't know how to reduce it further and still produce the failing asm. Differential Revision: http://reviews.llvm.org/D4351 llvm-svn: 212275
* fixed a few typos in commentsSanjay Patel2014-06-241-11/+9
| | | | llvm-svn: 211634
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-14/+15
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
| | | | llvm-svn: 205610
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Use SmallVectorImpl instead of SmallVector as method argument to avoid ↵Craig Topper2013-07-031-1/+1
| | | | | | specifying vector size. llvm-svn: 185513
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-1/+1
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-2/+2
| | | | llvm-svn: 182531
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-17/+1
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* This patch addresses bug 15031.Bill Schmidt2013-01-281-8/+24
| | | | | | | | | | | | | | | | | | | | | | The common code in the post-RA scheduler to break anti-dependencies on the critical path contained a flaw. In the reported case, an anti-dependency between the overlapping registers %X4 and %R4 exists: %X29<def> = OR8 %X4, %X4 %R4<def>, %X3<def,dead,tied3> = LBZU 1, %X3<kill,tied1> The unpatched code breaks the dependency by replacing %R4 and its uses with %R3, the first register on the available list. However, %R3 and %X3 overlap, so this creates two overlapping definitions on the same instruction. The fix is straightforward, preventing selection of a register that overlaps any other defined register on the same instruction. The test case is reduced from the bug report, and verifies that we no longer produce "lbzu 3, 1(3)" when breaking this anti-dependency. llvm-svn: 173706
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-3/+3
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-291-1/+1
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-151-1/+1
| | | | | | Clients can use the equivalent functions in MRI. llvm-svn: 165990
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | llvm-svn: 157885
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-15/+10
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-34/+16
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer2012-03-171-9/+11
| | | | llvm-svn: 152999
* CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse ↵Benjamin Kramer2012-03-161-7/+7
| | | | | | | | the cached value. No functionality change. llvm-svn: 152927
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-5/+5
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Handle regmasks in CriticalAntiDepBreaker.Jakob Stoklund Olesen2012-02-231-0/+14
| | | | llvm-svn: 151223
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-0/+2
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. llvm-svn: 151135
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-2/+2
| | | | llvm-svn: 133944
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-8/+6
| | | | | | No functional change was intended. llvm-svn: 133202
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-9/+6
| | | | llvm-svn: 132487
* Fix PostRA antidependence breaker.Andrew Trick2011-02-081-8/+46
| | | | | | | | Avoid using the same register for two def operands or and earlyclobber def and use operand. This fixes PR8986 and improves on the prior fix for rdar://problem/8959122. llvm-svn: 125089
* Fix an anti-dep breaker corner case.Andrew Trick2011-02-051-1/+0
| | | | | | | | | | | | | <rdar://problem/8959122> illegal register operands for UMULL instruction in cfrac nightly test I'm stil working on a unit test, but the case is: rx = movcc rx, r3 r2 = ldr r2, r3 = umull r2, r2 The anti-dep breaker should not convert this into an illegal instruction: r2, r2 = umull llvm-svn: 124932
* Fixes <rdar://problem/8612856>: During postRAsched, the antidependenceAndrew Trick2010-11-021-9/+27
| | | | | | | breaker needs to check all definitions of the antidepenent register to avoid multiple defs of the same new register. llvm-svn: 118032
* Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan'sBob Wilson2010-10-021-10/+14
| | | | | | | | | | | scheduling change in svn 115121. The CriticalAntiDepBreaker had bad liveness information. It was calculating the KillIndices for one scheduling region in a basic block, rescheduling that region so the KillIndices were no longer valid, and then using those wrong KillIndices to make decisions for the next scheduling region. I've not been able to reduce a small testcase for this. Radar 8502534. llvm-svn: 115400
* Fix a comment typo.Bob Wilson2010-09-101-1/+1
| | | | llvm-svn: 113653
* Anti-dependency breaking needs to be careful not to use reserved regsJim Grosbach2010-09-021-0/+2
| | | | llvm-svn: 112832
* Fix a use-after-free.Dan Gohman2010-07-261-2/+0
| | | | llvm-svn: 109468
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This timeBill Wendling2010-07-151-9/+16
| | | | | | make sure to allocate enough space in the std::vector. llvm-svn: 108449
* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-151-4/+2
| | | | llvm-svn: 108419
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