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* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-5/+5
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Handle regmasks in CriticalAntiDepBreaker.Jakob Stoklund Olesen2012-02-231-0/+14
| | | | llvm-svn: 151223
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-0/+2
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. llvm-svn: 151135
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-2/+2
| | | | llvm-svn: 133944
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-8/+6
| | | | | | No functional change was intended. llvm-svn: 133202
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-9/+6
| | | | llvm-svn: 132487
* Fix PostRA antidependence breaker.Andrew Trick2011-02-081-8/+46
| | | | | | | | Avoid using the same register for two def operands or and earlyclobber def and use operand. This fixes PR8986 and improves on the prior fix for rdar://problem/8959122. llvm-svn: 125089
* Fix an anti-dep breaker corner case.Andrew Trick2011-02-051-1/+0
| | | | | | | | | | | | | <rdar://problem/8959122> illegal register operands for UMULL instruction in cfrac nightly test I'm stil working on a unit test, but the case is: rx = movcc rx, r3 r2 = ldr r2, r3 = umull r2, r2 The anti-dep breaker should not convert this into an illegal instruction: r2, r2 = umull llvm-svn: 124932
* Fixes <rdar://problem/8612856>: During postRAsched, the antidependenceAndrew Trick2010-11-021-9/+27
| | | | | | | breaker needs to check all definitions of the antidepenent register to avoid multiple defs of the same new register. llvm-svn: 118032
* Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan'sBob Wilson2010-10-021-10/+14
| | | | | | | | | | | scheduling change in svn 115121. The CriticalAntiDepBreaker had bad liveness information. It was calculating the KillIndices for one scheduling region in a basic block, rescheduling that region so the KillIndices were no longer valid, and then using those wrong KillIndices to make decisions for the next scheduling region. I've not been able to reduce a small testcase for this. Radar 8502534. llvm-svn: 115400
* Fix a comment typo.Bob Wilson2010-09-101-1/+1
| | | | llvm-svn: 113653
* Anti-dependency breaking needs to be careful not to use reserved regsJim Grosbach2010-09-021-0/+2
| | | | llvm-svn: 112832
* Fix a use-after-free.Dan Gohman2010-07-261-2/+0
| | | | llvm-svn: 109468
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This timeBill Wendling2010-07-151-9/+16
| | | | | | make sure to allocate enough space in the std::vector. llvm-svn: 108449
* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-151-4/+2
| | | | llvm-svn: 108419
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-151-2/+4
| | | | | | get *very* large, but we only need it to be the size of thenumber of pregs. llvm-svn: 108411
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-53/+84
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-021-0/+1
| | | | | | for debug information. llvm-svn: 105324
* Update debug information when breaking anti-dependencies. rdar://7759363Jim Grosbach2010-06-011-1/+19
| | | | llvm-svn: 105300
* Remove trailing whitespaceJim Grosbach2010-05-141-3/+3
| | | | llvm-svn: 103807
* Make BreakAntiDependencies' SUnits argument const, and make the BeginDan Gohman2010-04-191-13/+13
| | | | | | and End arguments by-value rather than by-reference. llvm-svn: 101830
* Fix some more places where dbg_value affected codegen.Dale Johannesen2010-03-051-0/+4
| | | | llvm-svn: 97765
* Anti-dependency breaking needs to be careful regarding instructions withJim Grosbach2010-01-061-2/+7
| | | | | | multiple register definitions. llvm-svn: 92864
* 80 column and whitespace cleanupJim Grosbach2010-01-061-5/+6
| | | | llvm-svn: 92837
* Change errs() to dbgs().David Greene2010-01-041-5/+5
| | | | llvm-svn: 92490
* <rdar://problem/7453528>. Track only physical registers that are valid for ↵David Goodwin2009-12-091-3/+6
| | | | | | the target. llvm-svn: 90970
* Remove some old experimental code that is no longer needed. Remove ↵David Goodwin2009-11-201-1/+0
| | | | | | additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. llvm-svn: 89471
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-031-1/+2
| | | | | | registers that should be renamed. llvm-svn: 85939
* Break anti-dependence breaking out into its own class.David Goodwin2009-10-261-0/+539
llvm-svn: 85127
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