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path: root/llvm/lib/Analysis/TargetTransformInfo.cpp
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* [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]Anna Welker2019-12-181-4/+6
* Rename TTI::getIntImmCost for instructions and intrinsicsReid Kleckner2019-12-111-6/+6
* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-091-6/+6
* Sink all InitializePasses.h includesReid Kleckner2019-11-131-3/+4
* [TTI][LV] preferPredicateOverEpilogueSjoerd Meijer2019-11-061-0/+6
* [PGO][PGSO] TargetLowering/TargetTransformationInfo/SwitchLoweringUtils part.Hiroshi Yamauchi2019-10-311-3/+4
* [Alignment][NFC] getMemoryOpCost uses MaybeAlignGuillaume Chatelet2019-10-251-5/+5
* [NFC][TTI] Add Alignment for isLegalMasked[Load/Store]Sam Parker2019-10-141-4/+6
* recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure s...Zi Xuan Wu2019-10-121-2/+10
* [System Model] [TTI] Move default cache/prefetch implementationsDavid Greene2019-10-101-28/+0
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-10-091-0/+28
* Revert "[LoopVectorize][PowerPC] Estimate int and float register pressure sep...Jinsong Ji2019-10-081-10/+2
* [LoopVectorize][PowerPC] Estimate int and float register pressure separately ...Zi Xuan Wu2019-10-081-2/+10
* Revert "[SLP] avoid reduction transform on patterns that the backend can load...Martin Storsjo2019-10-071-53/+0
* [SLP] avoid reduction transform on patterns that the backend can load-combineSanjay Patel2019-10-051-0/+53
* [NFC][HardwareLoops] Update some iteratorsSam Parker2019-10-011-11/+6
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-3/+2
* [NFC] remove unused functionsGuillaume Chatelet2019-09-161-8/+0
* [LLVM][Alignment] Convert isLegalNTStore/isLegalNTLoad to llvm::AlignGuillaume Chatelet2019-09-051-2/+2
* [CostModel] Model all `extractvalue`s as free.Roman Lebedev2019-08-291-0/+2
* InferAddressSpaces: Move target intrinsic handling to TTIMatt Arsenault2019-08-141-0/+10
* [AMDGPU] Tune inlining parameters for AMDGPU targetDaniil Fukalov2019-07-171-0/+4
* Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareL...Jinsong Ji2019-07-091-32/+1
* [HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfi...Chen Zheng2019-07-091-1/+32
* [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware l...Chen Zheng2019-07-031-0/+7
* [HardwareLoops] NFC - move loop with irreducible control flow checking logic ...Chen Zheng2019-06-261-7/+11
* [HardwareLoops] NFC - move loop with irreducible control flow checking logic ...Chen Zheng2019-06-261-1/+9
* [ExpandMemCmp] Move all options to TargetTransformInfo.Clement Courbet2019-06-251-3/+3
* [NFC] move some hardware loop checking code to a common place for other using.Chen Zheng2019-06-191-0/+85
* [GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra b...Amara Emerson2019-06-171-0/+4
* [LV] Suppress vectorization in some nontemporal casesWarren Ristow2019-06-171-0/+10
* [CodeGen] Generic Hardware Loop SupportSam Parker2019-06-071-0/+6
* [CostModel] Add really basic support for being able to query the cost of the ...Craig Topper2019-05-281-0/+10
* [ARM] Implement TTI::getMemcpyCostSjoerd Meijer2019-04-301-0/+6
* [ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compres...Craig Topper2019-03-211-0/+8
* [TTI] Enable analysis of clib functions in getIntrinsicCosts. NFCI.Sjoerd Meijer2019-03-121-6/+9
* [LSR] Generate cross iteration indexesSam Parker2019-02-071-0/+4
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* Only promote args when function attributes are compatibleTom Stellard2019-01-161-0/+6
* [TTI] getOperandInfo - a broadcast shuffle means the result is OK_UniformValue Simon Pilgrim2018-11-141-0/+7
* [TTI] Make TargetTransformInfo::getOperandInfo static. NFCI.Simon Pilgrim2018-11-131-2/+1
* [TTI] Flip vector types in getShuffleCost SK_ExtractSubvector callSimon Pilgrim2018-11-091-1/+1
* [CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR3...Simon Pilgrim2018-11-091-2/+8
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-311-3/+6
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-141-3/+7
* revert 344472 due to failures.Dorit Nuzman2018-10-141-7/+3
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-141-3/+7
* [LoopVectorizer] Use TTI.getOperandInfo()Jonas Paulsson2018-10-051-43/+43
* Remove trailing spaceFangrui Song2018-07-301-9/+9
* [TargetTransformInfo] Add pow2 analysis for scalar constantsSimon Pilgrim2018-07-111-0/+6
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