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* [DebugInfo][Support] Replace DWARFDataExtractor size functionJames Henderson2020-01-132-4/+5
* This option allows selecting the TLS size in the local exec TLS model,KAWASHIMA Takahiro2020-01-132-0/+8
* [NFC] Update loop.decrement.reg intrinsic commentSam Parker2020-01-131-1/+3
* [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song2020-01-111-4/+0
* [Support] Optionally call signal handlers when a function wrapped by the the ...Alexandre Ganea2020-01-112-0/+17
* [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from R...Craig Topper2020-01-101-4/+0
* [LockFileManager] Make default waitForUnlock timeout a parameter, NFCVedant Kumar2020-01-101-1/+3
* [AArch64] Add isAuthenticated predicate to MCInstDescVedant Kumar2020-01-102-0/+11
* [CMake] Fix modules build after DWARFLinker reorganizationJonas Devlieghere2020-01-101-0/+7
* [AArch64] Add function attribute "patchable-function-entry" to add NOPs at fu...Fangrui Song2020-01-101-0/+3
* [FPEnv] Invert sense of MIFlag::FPExcept flagUlrich Weigand2020-01-101-4/+4
* [FPEnv] Generate constrained FP comparisons from clangUlrich Weigand2020-01-101-0/+41
* [MIR] Fix cyclic dependency of MIR formatterPeng Guo2020-01-103-9/+9
* [ThinLTO] Pass CodeGenOpts like UnrollLoops/VectorizeLoop/VectorizeSLPWei Mi2020-01-091-0/+4
* TableGen/GlobalISel: Fix pattern matching of immarg literalsMatt Arsenault2020-01-091-4/+9
* TableGen/GlobalISel: Add way for SDNodeXForm to work on timmMatt Arsenault2020-01-093-2/+35
* GlobalISel: Handle llvm.read_registerMatt Arsenault2020-01-093-2/+27
* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* GlobalISel: Move getLLTForMVT/getMVTForLLTMatt Arsenault2020-01-092-5/+9
* TableGen/GlobalISel: Address fixmeMatt Arsenault2020-01-091-0/+5
* [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assem...Eric Astor2020-01-092-5/+9
* [Support][NFC] Add a comment about the semantics of MF_HUGE_HINT flagBruno Ricci2020-01-091-0/+11
* [NFCI][LoopUnrollAndJam] Changing LoopUnrollAndJamPass to a functionWhitney Tsang2020-01-091-5/+2
* [ARM,MVE] Add missing IntrNoMem flag on IR intrinsics.Simon Tatham2020-01-091-14/+13
* [VE] Target stub for NEC SX-AuroraKazushi (Jam) Marukawa2020-01-091-1/+7
* [LoopUtils][NFC] Minor refactoring in getLoopEstimatedTripCount.Evgeniy Brevnov2020-01-091-0/+5
* [APFloat] Fix checked error assert failuresEhud Katz2020-01-091-1/+2
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-087-3/+106
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-087-106/+3
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-087-3/+106
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-087-106/+3
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-087-3/+106
* [Attributor][FIX] Carefully change invokes to calls (after manifest)Johannes Doerfert2020-01-081-0/+10
* [Attributor][FIX] Avoid dangling value pointers during code modificationJohannes Doerfert2020-01-082-1/+20
* [PowerPC]: Add powerpcspe target triple subarch componentJustin Hibbits2020-01-081-1/+3
* Recommit "[MachineVerifier] Improve verification of live-in lists."Jonas Paulsson2020-01-081-0/+3
* Revert "Merge memtag instructions with adjacent stack slots."Evgenii Stepanov2020-01-081-7/+0
* Revert "[JumpThreading] Thread jumps through two basic blocks"Kazu Hirata2020-01-081-5/+0
* Merge memtag instructions with adjacent stack slots.Evgenii Stepanov2020-01-081-0/+7
* [BranchAlign] Compiler support for suppressing branch alignPhilip Reames2020-01-082-0/+14
* [JumpThreading] Thread jumps through two basic blocksKazu Hirata2020-01-081-0/+5
* [ARM,MVE] Intrinsics for variable shift instructions.Simon Tatham2020-01-081-0/+7
* [ARM,MVE] Intrinsics for partial-overwrite imm shifts.Simon Tatham2020-01-081-0/+11
* [Intrinsic] Add fixed point division intrinsics.Bevin Hansson2020-01-084-1/+27
* [NFC] Move InPQueue into arguments of releaseNodeQiu Chaofan2020-01-081-5/+13
* [Dsymutil][Debuginfo][NFC] Reland: Refactor dsymutil to separate DWARF optimi...Alexey Lapshin2020-01-084-1/+586
* AArch64: add missing Apple CPU names and use them by default.Tim Northover2020-01-081-0/+18
* [X86] Adding fp128 support for strict fcmpWang, Pengfei2020-01-081-0/+6
* [SCEV] get more accurate range for AddExpr with wrap flag.czhengsz2020-01-071-0/+1
* [AArch64][GlobalISel] Fold a chain of two G_PTR_ADDs of constant offsets.Amara Emerson2020-01-072-1/+17
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